Maxim Integrated MAX32665 - Table 4-73: Bluetooth LDO Delay Count Register; Table 4-74: General Purpose 0 Register; Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 112 of 457
Table 4-73: Bluetooth LDO Delay Count Register
Bluetooth LDO Delay Count
GCR_BTLE_LDODCR
[0x0078]
Bits
Field
Access
Reset
Description
31:29
-
RO
0
Reserved
28:20
ldotxdlycnt
R/W
0x01B
Bluetooth LDOTX Delay Count
Not used.
19:17
-
RO
0
Reserved
16:8
ldorxdlycnt
R/W
0x01B
Bluetooth LDORX Delay Count
Not used.
7:0
bypdlycnt
R/W
0x28
Bluetooth LDO Bypass Delay Count
Not used.
Table 4-74: General Purpose 0 Register
General Purpose 0
GCR_GPR0
[0x0080]
Bits
Field
Access
Reset
Description
31:0
gpr0
R/W
0
User-defined register RAM
Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register
Arm Peripheral Bus Asynchronous Bridge Select
GCR_APB_ASYNC
[0x0084]
Bits
Field
Access
Reset
Description
31:4
-
RO
0
Reserved
Do not modify this field.
3
apbasyncpt
R/W
0
Pulse Trains Peripheral Bus Select
This peripheral can be connected to the APB PCLK domain or a 7.3728MHz bus
can be used. It takes 3 cycles of the 7.3728MHz clock to switch PCLK or 3 cycles
of the PCLK clock to switch to 7.37MHz clock. After switching, ensure enough
time before accessing the peripheral registers.
0: Peripheral is accessed on the PCLK bus.
1: Peripheral is accessed on the 7.3728MHz bus.
2
apbasyncI2C2
R/W
0
I2C2 Peripheral Bus Select
The access for this peripheral can be performed via one of two different
peripheral bus configurations. The system PCLK can be used as any of the other
system peripherals that are connected to the APB PCLK domain or a 7.3728MHz
bus can be used. It takes 3 cycles of the 7.3728MHz clock to switch PCLK or 3
cycles of the PCLK clock to switch to 7.37MHz clock. After switching, ensure
enough time before accessing the peripheral registers.
0: PCLK bus selected
1: 7.3728MHz bus selected
1
apbasyncI2C1
R/W
0
I2C1 Peripheral Bus Select
The access for this peripheral can be performed via one of two different
peripheral bus configurations. The system PCLK can be used as any of the other
system peripherals that are connected to the APB PCLK domain or a 7.3728MHz
bus can be used. It takes 3 cycles of the 7.3728MHz clock to switch PCLK or 3
cycles of the PCLK clock to switch to 7.37MHz clock. After switching, ensure
enough time before accessing the peripheral registers.
0: PCLK bus selected
1: 7.3728MHz bus selected