MAX32665-MAX32668 User Guide
Maxim Integrated Page 303 of 457
I
2
C FIFO Data Register
Reads from this register pops data off the RX FIFO. Writes to this register pushes
data onto the TX FIFO. Reading from an empty RX FIFO returns 0xFF. Writes to a full
TX FIFO are ignored.
Table 13-18: I
2
C Master Mode Control Register
MCODE
These bits set the master code used in Hs-mode operation
Slave Extended Addressing Enable
0: Send a 7-bit address to the slave
1: Send a 10-bit address to the slave
Send STOP Condition
1: Send a STOP Condition at the end of the current transaction.
Note: This bit is automatically cleared by hardware when the STOP condition begins.
Send Repeated START Condition
After sending data to a slave, the master may send another START to retain control
of the bus.
1: Send a Repeated START condition to Slave instead of sending a STOP condition
at the end of the current transaction.
Note: This bit is automatically cleared by hardware when the repeated START
condition begins.
Start Master Mode Transfer
1: Start Master Mode Transfer
Note: This bit is automatically cleared by hardware when the transfer is completed
or aborted.
Table 13-19: I
2
C SCL Low Control Register
Clock Low Time
In Master Mode, this configures the SCL low time.
Note: 0 is not a valid setting for this field.
Table 13-20: I
2
C SCL High Control Register
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