MAX32665-MAX32668 User Guide
Maxim Integrated Page 38 of 457
The alias area for the SRAM bit-banding is located beginning at 0x2200 0000 and is a total of 32MB maximum, which allows
the entire 1MB bit banding area to be accessed. Each 32-bit (4 byte aligned) address location in the bit-banding alias area
translates into a single bit access (read or write) in the bit-banding primary area. Reading from the location performs a
single bit read, while writing either a 1 or 0 to the location performs a single bit set or clear.
Note: The Arm Cortex-M4 core translates the access in the bit-banding alias area into the appropriate read cycle (for a single
bit read) or a read-modify-write cycle (for a single bit set or clear) of the bit-banding primary area. This means that bit-
banding is a core function (i.e., not a function of the SRAM memory interface layer or the AHB bus layer), and thus is only
applicable to accesses generated by the core itself. Reads/writes to the bit-banding alias area by other (non-Arm-core) bus
masters will not trigger a bit-banding operation and will instead result in an AHB bus error.
The SRAM area on the MAX32665—MAX32668 can be used to contain executable code. Code stored in the SRAM is
accessed directly for execution (using the system bus) and is not cached. The SRAM is also where the Arm Cortex-M4 stack
must be located, as it is the only general-purpose SRAM memory on the device. A valid stack location inside the SRAM must
be set by the system exception table (which is, by default, stored at the beginning of the internal flash memory).
The MAX32665—MAX32668 specific AHB Bus Masters can access the SRAM to use as general storage or working space.
Specifically, in the case of the USB interface, SRAM memory area can be used to store the descriptor table for the endpoint
buffers as well as the endpoint buffers themselves.
3.2.3 Peripheral Space
The peripheral space area of memory is intended for mapping of control registers, internal buffers/working space, and
other features needed for the firmware control of non-core peripherals. It is defined from byte address range 0x4000 0000
to 0x5FFF FFFF (0.5GB maximum). On the MAX32665—MAX32668, all device-specific module registers are mapped to this
memory area, as well as any local memory buffers or FIFOs which are required by modules.
As with the SRAM region, there is a dedicated 1MB area at the bottom of this memory region (from 0x4000 0000 to
0x400F FFFF) that is used for bit-banding operations by the Arm core. Four-byte-aligned read/write operations in the
peripheral bit-banding alias area (32MB in length, from 0x4200 0000 to 0x43FF FFFF) are translated by the core into
read/mask/shift or read/modify/write operation sequences to the appropriate byte location in the bit-banding area.
Note: The bit-banding operation within peripheral memory space is, like bit-banding function in SRAM space, a core
remapping function. As such, it is only applicable to operations performed directly by the Arm core. If another memory bus
master accesses the peripheral bit-banding alias region, the bit-banding remapping operation will not take place. In this
case, the bit-banding alias region will appear to be a non-implemented memory area (causing an AHB bus error).
On the MAX32665—MAX32668, access to the region that contains most peripheral registers (0x4000 0000 to 0x400F FFFF)
goes from the AHB bus through an AHB-to-APB bridge. This allows the peripheral modules to operate on the lower power
APB bus matrix. This also ensures that peripherals with slower response times do not tie up bandwidth on the AHB bus,
which must necessarily have a faster response time since it handles main application instruction and data fetching.
A secondary region within the peripheral memory space (0x0400B 0000 to 0x400F FFFF) allows peripherals that require
more rapid data transfer to handle this data transfer using their own local AHB slave instances (instead of going indirectly
through the AHB-to-APB bridge). This allows peripherals which have FIFOs or other functions requiring large amounts of
data to be transferred quickly (such as the SD/SDIO/SDHC/MMC or communications peripherals like SPI) to benefit from the
more rapid data transfer rate of the AHB bus.
3.2.4 External RAM Space
The external RAM space area of memory is intended for use in mapping off-chip external memory and is defined from byte
address range 0x6000 0000 to 0x9FFF FFFF (1GB maximum). The MAX32665—MAX32668 implements support for external
SPI SRAM. The external SPI SRAM SPIXR interface is mapped to byte address 0x8000 000 to 0x9FFF FFFF (up to 512MB).
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