Maxim Integrated MAX32665 - Instruction Cache Controller; Enabling ICC0;ICC1;SFCC; Figure 4-6: MAX32665-MAX32668 Cache Controllers Control

MAX32665-MAX32668 User Guide
Maxim Integrated Page 63 of 457
Figure 4-6: MAX32665—MAX32668 Cache Controllers Control
I D
GCR_SCON
dcache_dis
SPIXR CACHE
BYPAS S
ARM
®
Cortex
®
-M4
CPU1
AHB
INTERNAL
ROM0
INSTRUCTION CACHE
CONTROLLER 0 (ICC0)
SPIXF CACHE
CONTROLLER (SFCC)
SPIXR
INTERFACE
EXTERNAL
SPI-XIP RAM
SYSTEM BUS
MDIU
SPIXF
INTERFACE
EXTERNAL
SPI-XIP FLA SH
LINE BUFFER
16KB
INSTRUCTION
CACHE
512KB INTERNAL
FLASH
MEMORY
LINE BUFFER
16KB
INSTRUCTION
CACHE
SPIXR CACHE
CONTROLLER (SRCC)
LINE BUFFER
16KB EXTERNAL
SPI RAM MEMORY
CACHE
ARM
®
Cortex
®
-M4
CPU0
I D
INTERNAL
ROM1
INSTRUCTION CACHE
CONTROLLER 1 (ICC1)
512KB INTERNAL
FLASH
MEMORY
LINE BUFFER
16KB
INSTRUCTION
CACHE
CACHE BUS
ERROR
CORRECTION
4.5 Instruction Cache Controller
ICC0, ICC1 and SFCC are independent cache controllers and each is controlled directly using their respective register set.
4.5.1 Enabling ICC0/ICC1/SFCC
Perform the following steps to enable ICC0 or ICC1.
1. Set PWRSEQ_LPMEMSD.icachensd to 0 to ensure the cache power is on.
2. Set ICCn_CACHE_CTRL.enable to 1.
3. Read ICCn_CACHE_CTRL.ready until it returns 1.