Maxim Integrated MAX32665 - Table 23-27: TRNG Control Register (Base Address 0 X400 B_5000); Table 23-28: TRNG Data Register (Base Address 0 X400 B_5000)

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Table 23-27: TRNG Control Register (Base address 0x400B_5000)
TRNG Control Register
TRNG_CN
[0x0000]
BITS
NAME
ACCESS
RESET
DESCRIPTION
31:7
-
RO
1
Reserved for Future Use
Do not modify this field from its default value.
6
aeskg
R/W
0
AES Key Generate
When enabled, the key for securing NVSRAM is generated and transferred to the
secure key register automatically without user visibility or intervention. This bit is
cleared by hardware once the key has been transferred to the secure key register.
5
rng_is
RO
0
Random Number Ready Status
This bit is set when a new 32 bit random number is available in TRNG_DATA. This bit is
cleared by hardware if all the random words have been read. It is needed to poll this
bit before reading the TRNG Data Register
4
rng_i4s
RO
0
128-bit Random Number Ready Status
This bit is set when a new 128 bit random number is ready to be read (using 4
consecutive reads of TRNG_DATA. When set, an interrupt will be generated if
TRNG_CN.rng_ie = 1. This bit is cleared by setting TRNG_CN.rng_isc.
3
rng_isc
W
0
Random Number Interrupt Status Clear
Setting this bit to 1 clears TRNG_CN.rng_i4s and acknowledges the interrupt, if
enabled. This it is a write only bit and always reads as zero.
2
rng_ie
R/W
0
Random Number Interrupt Enable
This bit enables an interrupt to be generated when TRNG_CN.rng_i4s = 1.
1:0
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
Table 23-28: TRNG Data Register (Base address 0x400B_5000)
MAA Word Size Register
TRNG_DATA
[0x0004]
BITS
NAME
ACCESS
RESET
DESCRIPTION
31:0
data
RO
0
TRNG Data
The function of this register is dependent on the rng_is and rng_i4s bits