Maxim Integrated MAX32665 - Register Details; Table 19-3: Watchdog Timer Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 384 of 457
19.10 Register Details
Table 19-3: Watchdog Timer Control Register
Watchdog Timer Control Register
WDTn_CTRL
[0x0000]
Bits
Name
Access
Reset
Description
31
rst_flag
R/W
0
WDT Reset Flag
If set a watchdog system reset occurred. This field is set to 0 on a POR and is not
affected by other resets.
0: Watchdog did not cause reset event.
1: Watchdog reset occurred.
30:12
-
RO
0
Reserved for Future Use
Do not modify this field from its reset value.
11
rst_en
R/W
0
WDT Reset Enable
Enable/disable system reset if the rst_period expires. This field is set to 0 on a
POR and is not affected by other resets.
0: Disabled
1: Enabled.
10
int_en
R/W
0
WDT Interrupt Enable
Enable or disable the watchdog interrupt. This field is set to 0 on a POR and is
not affected by other resets.
0: Disabled
1: Enabled
9
int_flag
R/W1C
0
WDT Interrupt Flag
If set, the watchdog interrupt period has occurred. This field is set to 0 on a POR
and is not affected by other resets.
0: IRQ not pending
1: Interrupt period expired. Generates and IRQ if WDTn_CTRL.int_en=1.
8
wdt_en
R/W
0
WDT Enable
Enable or disable the watchdog timer. To enable the watchdog timer, the
following sequence of writes must be performed. This field is set to 0 on a POR
and is not affected by other resets.
1) Write WDTn_RST: 0x0000 00A5
2) Write WDTn_RST: 0x0000 005A
3) Write wdt_en: 0x1
0: Disabled
1: Enabled