MAX32665-MAX32668 User Guide
Maxim Integrated Page 145 of 457
The format of the header is shown in Table 8-1. If the transaction generates receive data, this data is pushed into the SPI.
The Receive FIFO is SPIXFC_FIFO_RX.
A complete access sequence to a SPI device is made up of one or more transactions. In some cases, the slave select signal
remains asserted across several transactions. In other cases, the access sequence defined by the slave device might require
de-assertion of the slave selection in the middle of the access sequence. In general, any part of the access sequence that
requires a change in direction, width, or timing, requires another transaction. Interrupt logic is provided to allow efficient
servicing of the SPI Master functionality by firmware.
Table 8-1: SPI Header Format
Reserved for Future Use. This header field should always be
set to 0b00.
0: Maintain assertion of slave select after
transaction.
1: De-assert slave select at the
completion of transaction
Reserved for Future Use. This header field should always be
set to 0b00.
Number of SDIO pins to use for the transaction.
0x00: Single I/O mode
0x01: Dual I/O mode
0x02: Quad I/O mode
0x03: Invalid
Size of transaction in terms of units.
0x00: 32
0x01: 1
0x02: 2
…
0x0F: 15
Defines units to use when interpreting the size field. Bit
transactions are available only for Tx (that is, Direction = 1
transactions).
0: Bits
1: Bytes
2: Pages (See the SPIXFC_CFG.pgsz field
for page size definition)
Defines direction of information transfer. For headers that
do not define a transmission (that is, direction = None or Rx),
no payload is required. Conversely, headers that do not
define a reception (that is,. direction = None or Tx), result in
no data pushing into the Receive FIFO.
0: None
1: Tx
2: Rx
3: Both
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