MAX32665-MAX32668 User Guide
Maxim Integrated Page 146 of 457
8.2.1.1.3 Sample SPIXF Master Controller Example
Here is an example how to set up the Master Controller:
1. Configure the SPIXF Master Controller mode, number of bytes per page (see SPIXFC_CFG.pgsz and Note below),
SCK high and low values, and Slave Select (SS) active timing and inactive timing.
a. Example:
i. SPIXFC_CFG.mode = 0b00 SPI Mode 0
ii. SPIXFC_CFG.pgsz = 0b00 Page size = four bytes
iii. SPIXFC_CFG.loclk = 0b01 SCK low time = 1 system clock period
iv. SPIXFC_CFG.hiclk = 0b01 SCK high time = 1 system clock period
v. SPIXFC_CFG.ssact = 0b10 SS Active time = 4 system clock periods
vi. SPIXFC_CFG.inact = 0b10 SS Inactive stretch time = 8 system clock periods
2. Configure the Almost Empty and Almost Full levels for monitoring the FIFOs.
a. Example:
i. SPIXFC_FIFO_CTRL.tfifolvl = 0x8 Almost Empty = 8
ii. SPIXFC_FIFO_CTRL.rfifolvl = 0xC Almost Full = 12
3. Enable the Transmit and Receive FIFOs as well as the feedback clock.
i. SPIXFC_GEN_CTRL.rfifoen = 1 Receive FIFO enabled
ii. SPIXFC_GEN_CTRL.tfifoen = 1 Transmit FIFO enabled
4. Write the header then payload data to the Transmit FIFO (SPIXFC_FIFO_TX) to send a command to configure the
SPI flash for configuration or programming. More than one command may be loaded to the FIFO.
5. Initialize the SPIXF Master Controller interrupt flags by clearing the SPIXFC_INT_FL register.
6. Set the interrupt enables for Transmit FIFO stalled and almost empty to make sure that the Transmit FIFO does not
stall the AHB bus.
7. Write to the SPIXF Master Controller enable bit to start the transmission (SPIXFC_GEN_CTRL.enable = 1).
8. Monitor the receive stalled interrupt status flag to know when data is available in the Receive FIFO if data is
received by this command.
9. Monitor the SPIXFC_INT_FL.txrdy for indication that the command has completed.
10. Repeat steps 6 through 9 to monitor multiple commands to the SPI flash if necessary.
Note: Page size is used if enabled by the SPIXF Master Controller header to configure the SPIXF Master Controller for larger
transaction packet sizes (not to be confused with the SPI flash page size).
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