Maxim Integrated MAX32665 - Table 8-42: SRCC Invalidate Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 180 of 457
SRCC Cache Control Register
SRCC_CACHE_CTRL
[0x0100]
Bits
Name
Access
Reset
Description
15:3
-
R/W
-
Reserved for Future Use
Do not modify this field.
2
cwfst_dis
R/W
0
Critical Word First (CWF) Disable
Setting this field to 1 disables Critical Word First operation. When CWF is disabled,
the cache fills the cache line before sending the data to the Arm Cortex core.
When CWF is enabled, any data fetch that results in a cache miss immediately
sends the data read to the Arm Cortex core prior to filling the cache line.
0: Enable Critical Word First.
1: Critical Word First Disabled.
Note: This field is only writable when the EMCC is disabled
(SRCC_CACHE_CTRL.enable = 0).
1
write_alloc
R/W
0
Write Allocate Enable
Set this field to enable write allocate for the cache. When this is enabled, writes
to the memory update the external memory and the cache line associated with
the write is filled from the external memory. Disabling write allocate, default
mode, performs a write to the external memory on any write operation, but the
associated cache line is not refilled. When disabled, writes to successive memory
locations are more efficient.
0: Write allocate disabled (default)
1: Write allocate enabled.
Note: The EMCC is a write-through cache resulting in any write to the external
memory performing an immediate write to the external device.
0
enable
R/W
0
Enable
Set this field to 1 to enable the cache. Setting this field to 0 automatically
invalidates the cache contents. When this cache is disabled, reads are handled by
the line fill buffer.
0: Disable Cache
1: Enable Cache
Table 8-42: SRCC Invalidate Register
SRCC Invalidate Register
SRCC_INVALIDATE
[0x0700]
Bits
Name
Access
Reset
Description
31:0
-
WO
-
Invalidate
Any write to this register of any value invalidates the cache.