MAX32665-MAX32668 User Guide
Maxim Integrated Page 174 of 457
SPIXR DMA Control Register
Clear the TX FIFO
Set this field to 1 to clear the TX FIFO and all TX FIFO related flags in the
SPIXR_INT_FL register. When the TX FIFO is cleared, the
SPIXR_INT_FL.tx_fifo_empty flag is set by hardware.
1: Clear the TX FIFO and any pending TX FIFO flags in SPIXR_INT_FL. This
should be done when the TX FIFO is inactive.
Note: Writing a 0 has no effect.
TX FIFO Enabled
Set to 1 to enable the TX FIFO.
0: TX FIFO disabled
1: TX FIFO enabled
Reserved for Future Use
Do not modify this field.
TX FIFO Threshold Level
When the TX FIFO has fewer than this field, a DMA request is triggered and the
SPIXR_INT_FL.tx_level interrupt flag is set.
For all read-only fields, writes have no effect.
Table 8-32. SPIXR Interrupt Status Flag Register
SPIXR Interrupt Status Flag Register
RX FIFO Underrun Flag
Set when a read is attempted from an empty RX FIFO.
RX FIFO Overrun Flag
Set if SPI is in Slave Mode, and a write to a full RX FIFO is attempted. If the SPI is
in Master Mode, this bit is not set as the SPI stalls the clock until data is read
from the RX FIFO
TX FIFO Underrun Flag
Set if SPI is in Slave Mode, and a read from empty TX FIFO is attempted. If SPI is
in Master Mode, this bit is not set as the SPI stalls the clock until data is written
to the empty TX FIFO.
TX FIFO Overrun Flag
Set when a write is attempted to a full TX FIFO.
Master Data Transmission Done Flag
Set if SPI is in Master Mode, and all transactions have completed.
Reserved for Future Use
Do not modify this field.
Slave Mode Transaction Abort Detected Flag
Set if the SPI is in Slave Mode, and SS is deasserted before a complete character
is received.
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