Maxim Integrated MAX32665 - Table 8-32. SPIXR Interrupt Status Flag Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 174 of 457
SPIXR DMA Control Register
SPIXR_DMA
[0x001C]
Bits
Name
Access
Reset
Description
7
tx_fifo_clear
WO
0
Clear the TX FIFO
Set this field to 1 to clear the TX FIFO and all TX FIFO related flags in the
SPIXR_INT_FL register. When the TX FIFO is cleared, the
SPIXR_INT_FL.tx_fifo_empty flag is set by hardware.
1: Clear the TX FIFO and any pending TX FIFO flags in SPIXR_INT_FL. This
should be done when the TX FIFO is inactive.
Note: Writing a 0 has no effect.
6
tx_fifo_en
R/W
0
TX FIFO Enabled
Set to 1 to enable the TX FIFO.
0: TX FIFO disabled
1: TX FIFO enabled
5
-
R/W
0
Reserved for Future Use
Do not modify this field.
4:0
tx_fifo_level
R/W
0x10
TX FIFO Threshold Level
When the TX FIFO has fewer than this field, a DMA request is triggered and the
SPIXR_INT_FL.tx_level interrupt flag is set.
For all read-only fields, writes have no effect.
Table 8-32. SPIXR Interrupt Status Flag Register
SPIXR Interrupt Status Flag Register
SPIXR_INT_FL
[0x0020]
Bits
Name
Access
Reset
Description
31:16
-
R/W1C
0
Reserved for Future Use
15
rx_und
R/W1C
0
RX FIFO Underrun Flag
Set when a read is attempted from an empty RX FIFO.
14
rx_ovr
R/W1C
0
RX FIFO Overrun Flag
Set if SPI is in Slave Mode, and a write to a full RX FIFO is attempted. If the SPI is
in Master Mode, this bit is not set as the SPI stalls the clock until data is read
from the RX FIFO
13
tx_und
R/W1C
0
TX FIFO Underrun Flag
Set if SPI is in Slave Mode, and a read from empty TX FIFO is attempted. If SPI is
in Master Mode, this bit is not set as the SPI stalls the clock until data is written
to the empty TX FIFO.
12
tx_ovr
R/W1C
0
TX FIFO Overrun Flag
Set when a write is attempted to a full TX FIFO.
11
m_done
R/W1C
0
Master Data Transmission Done Flag
Set if SPI is in Master Mode, and all transactions have completed.
10
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
9
abort
R/W1C
0
Slave Mode Transaction Abort Detected Flag
Set if the SPI is in Slave Mode, and SS is deasserted before a complete character
is received.