MAX32665-MAX32668 User Guide
Maxim Integrated Page 329 of 457
16. Timers
Multiple 32-bit, reloadable timers are provided. Each timer provides multiple operating modes:
• One-Shot: Timer counts up to terminal value then halts.
• Continuous: Timer counts up to terminal value then repeats.
• Counter: Timer counts input edges received on timer input pin.
• Pulse Width Modulated (PWM) / PWM Differential.
• Capture: Captures a snapshot of the current timer count when timer input edge transitions.
• Compare: Timer pin toggles when timer exceeds terminal count.
• Gated: Timer increments only when timer input pin is asserted.
• Capture/Compare: Timer counts when timer input is asserted, captures timer count when input is deasserted.
The MAX32665–MAX32668 provide six instances of the timer peripheral (TMR0, TMR1, TMR2, TMR3, TMR3, TMR5).
16.1 Features
• 32-bit reload counter
• Programmable prescaler with values from 1 to 4096
• Non-overlapping PWM output generation with configurable off-time
• Capture, compare, and capture/compare capability
• Timer pin available as alternate function
• Configurable Input pin for event triggering, clock gating, or capture signal
• Timer output pin for event output and PWM signal generation
• Independent interrupt
16.2 Basic Operation
The timer modes operate by incrementing the TMRn_CNT register, driven by either the timer clock, an external stimulus on
the timer pin, or a combination of both. The TMRn_CNT register is always readable, even while the timer is enabled and
counting.
Each timer mode has a user-configurable timer period, which terminates on the timer clock cycle following the end of timer
period condition. Each timer mode has a different response at the end of a timer period, which can include changing the
state of the timer pin, capturing a timer value, reloading TMRn_CNT with a new starting value, or disabling the counter. The
end of a timer period will always set the corresponding interrupt bit and can generate an interrupt, if enabled.
In most modes the timer peripheral automatically sets TMRn_CNT to 0x0000 0001 at the end of a timer period, but
TMRn_CNT is set to 0x0000 0000 following a system reset. This means the first timer period following a system reset will be
one timer clock longer than subsequent timer periods if TMRn_CNT is not initialized to 0x0000 0001 during the timer
configuration step.
Clocking of timer functions is driven by the timer clock frequency, f
CNT_CLK
. The timer clock frequency is a user-configurable,
division of the system peripheral clock, PCLK. Each timer has an independent prescaler, allowing timers to operate at
different frequencies. The prescaler can be set from 1 to 4096 using the TMRn_CN.pres3:TMRn_CN.pres fields. Unless
otherwise mentioned, the timer clock is generated as follows:
Equation 16-1: Timer Peripheral Clock Equation
Application firmware writes to the timer registers and external events on timer pins will be asynchronous events to the
slower timer clock frequency. These events are latched on the next rising edge of the timer clock. Since it is not possible to
observe the timer clock directly, input events may have up to 0.5 timer clock delay before being recognized.
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