MAX32665-MAX32668 User Guide
Maxim Integrated Page 402 of 457
21. USB 2.0 High-Speed (USBHS) Host Interface with PHY
The microcontroller includes one Universal Serial Bus (USB) Host communications peripheral with a USB physical interface
(PHY). The USB Host is USB 2.0 High-Speed (USBHS) compliant, capable of transfers at 480Mbps. It supports Host mode with
12 USB buffers called endpoints.
The following features are supported:
• USB Device Mode
• USB 2.0 Full Speed (FS) 12Mbps transfers
• USB 2.0 Hi-Speed (HS) 480Mbps transfers
• Bulk transfers
• Isochronous transfers
• 11 endpoints plus Endpoint 0, each with dedicated FIFOs
• Packet splitting and combining
• High bandwidth IN and OUT Isochronous endpoints
Each endpoint has an associated FIFO with the following sizes:
• Endpoint 0 FIFO: 64 bytes deep
• Endpoints 1 through 7 FIFOs: 512 bytes deep
• Endpoints 8 and 9 FIFOs: 2048 bytes deep
• Endpoints 10 and 11 FIFOs: 4096 bytes deep
Supported interrupts include:
• Interrupts for each IN endpoint from Endpoint 0 to Endpoint 11
• Interrupts for each OUT endpoint from Endpoint 1 to Endpoint 11
• Start of Frame (SOF)
• RESET bus state
• RESUME bus state
• SUSPEND Mode bus state
• STALL sent
• Control byte received
• Control transfer ended early
• Packet transmitted
• Packet received
• Data underrun
• Data overrun
• Invalid token received
• Empty data packet sent
This chapter includes a simplified description of USB bus states. Refer to the USB 2.0 Specification for a complete
description of USB operation.
The USB device hardware behavior is controlled by the internal serial interface engine (SIE). The SIE is a small control
processor that manages the USB port’s behavior. When referring to behavior of the USB hardware, it is the SIE doing the
work.
21.1 Instances
There is one instance of the peripheral.
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