MAX32665-MAX32668 User Guide
Maxim Integrated Page 266 of 457
Parity Enable
If parity is enabled, parity is generated and verified based on the
UARTn_CTRL0.parity_mode field.
0: No parity checking or generation.
1: Parity generation and checking is enabled.
UART Enable
Enabling the UART activates the bit rate generator. Setting this field to 0 disables the
UART, flushes the Transmit FIFO and the Receive FIFO and disables the bit rate
generator.
0: UART disabled. The Receive FIFO and the Transmit FIFO are flushed, and the bit
rate generator is off.
1: UART enabled and bit rate generator is enabled.
Table 12-5: UART Control 1 Register
UART Control 1 Register 1
Reserved for Future Use
Do not modify this field.
RTS Receive FIFO Threshold Level
When the Receive FIFO level is equal to or greater than this value, de-assert RTS
output signal to inform the transmitting UART to stop sending data. Valid values are 1
to 32.
Reserved for Future Use
Do not modify this field.
Transmit FIFO Threshold Level
When the Transmit FIFO level is less than or equal to this value, set
UARTn_INT_FL.tx_fifo_lvl interrupt flag. Valid values are 1 to 32. Set this field greater
than 1 to avoid a stall condition when transmitting UART data.
Note: See Table 12-1: UART Interrupt Conditions for description.
Reserved for Future Use
Do not modify this field.
Receive FIFO Threshold Level
When the Receive FIFO level is equal to or greater than this value, the hardware sets
the UARTn_INT_FL.rx_fifo_lvl interrupt flag is set. Valid values are 1 to 32. Set this field
to less than 32 to avoid a Receive FIFO overrun condition.
Note: See Table 12-1: UART Interrupt Conditions for description.
Table 12-6: UART Status Register
Reserved for Future Use
Do not modify this field.
Number of characters in the Transmit FIFO
Read this field to determine the number of characters in the transmit FIFO.
Reserved for Future Use
Do not modify this field.
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