Maxim Integrated MAX32665 - I 2 C Interrupt Sources; TX FIFO and RX FIFO

MAX32665-MAX32668 User Guide
Maxim Integrated Page 288 of 457
13.4.8 I
2
C Interrupt Sources
The I
2
C controller has a very flexible interrupt generator that generates an interrupt signal to the Interrupt Controller on
any of several events. On recognizing the I
2
C interrupt, firmware determines the cause of the interrupt by reading the I
2
C
Interrupt Flags registers I2Cn_INT_FL0 and I2Cn_INT_FL1. Interrupts can be generated for the following events:
• Transaction Complete (Master/Slave)
• Address NACK received from slave (Master)
• Data NACK received from slave (Master)
• Lost arbitration (Master)
• Transaction timeout (Master/Slave)
• FIFO is empty, not empty, full to configurable threshold level (Master/Slave)
• TX FIFO locked out because it is being flushed (Master/Slave)
• Out of sequence START and STOP conditions (Master/Slave)
• Sent a NACK to an external master because the TX or RX FIFO was not ready (Slave)
• Address ACK or NACK received (Master)
• Incoming address match (Slave)
• TX Underflow or RX Overflow (Slave)
Interrupts for each event can be enabled or disabled by setting or clearing the corresponding bit in the I2Cn_INT_EN0 or
I2Cn_INT_EN1 interrupt enable register.
Note: Disabling the interrupt does not prevent the corresponding flag from being set by hardware but does prevent an IRQ
when the interrupt flag is set.
Note: Prior to enabling an interrupt, the status of the corresponding interrupt flag should be checked and, if necessary,
serviced or cleared. This prevents a previous interrupt event from interfering with a new I
2
C communications session.
13.4.9 TX FIFO and RX FIFO
There are separate transmit and receive FIFOs, TX FIFO and RX FIFO. Both are accessed using the FIFO Data register
I2Cn_FIFO. Writes to this register enqueue data into the TX FIFO. Writes to a full TX FIFO have no effect. Reads from
I2Cn_FIFO dequeue data from the RX FIFO. Writes to a full TS FIFO have no effect, and reads from an empty RX FIFO return
0xFF.
The TX and RX FIFO will only read or write one byte at a time. Transactions larger than 8 bits can still be performed,
however. A 16- or 32-bit write to the TX FIFO stores just the lowest 8 bits of the write data. A 16- or 32-bit read from the RX
FIFO will have the valid data in the lowest 8 bits and 0’s in the upper bits. In any case, the TX and RX FIFOs will only accept 8
bits at a time for either reads or a writes.
To offload work from the CPU, the DMA can read and write to each FIFO. See section I2C DMA Control for more information
on configuring the DMA.