MAX32665-MAX32668 User Guide
Maxim Integrated Page 287 of 457
If the TX FIFO is not ready (I2Cn_TX_CTRL1.txrdy = 0) and the I
2
C controller receives a data read request from the master,
the hardware automatically sends a NACK at the end of the first address byte. The setting of the Do Not Respond field is
ignored by the hardware in this case because the only opportunity to send a NACK for an I
2
C read transaction is after the
address byte.
13.4.7.2 Slave Receiver
The device will operate as a slave receiver when the received address matches the device slave address with the R/W bit set
to 0. The external master is writing to the slave.
Program flow for a receive operation is as follows:
1. With I2Cn_CTRL0.i2cen = 0, initialize all relevant registers.
2. Set I2Cn_CTRL0.i2cen = 1.
a. If an address match with R/W=0 occurs, and the RX FIFO is empty, the peripheral will respond with an ACK
and the I2Cn_INT_FL0.ami flag will be set.
b. If the RX FIFO is not empty, then depending on the value of I2Cn_RX_CTRL0.dnr, the peripheral will NACK
either the address byte (I2Cn_RX_CTRL0.dnr = 1) or the first data byte (I2Cn_RX_CTRL0.dnr = 0).
3. Wait for I2Cn_INT_FL0.ami =1, either by polling or by enabling the I2Cn_INT_FL0.wrami interrupt to the CPU. Once
a successful address match occurs, hardware will set I2Cn_INT_FL0.ami =1.
4. Read I2Cn_CTRL0.read to determine whether the transaction is a transmit (I2Cn_CTRL0.read = 1) or receive
(I2Cn_CTRL0.read = 0) operation. In this case we assume I2Cn_CTRL0.read = 0, indicating receive. At this point, the
device will begin receiving data into the RX FIFO.
5. Clear I2Cn_INT_FL0.ami, and while the master keeps sending data, I2Cn_INT_FL0.donei will remain 0 and software
should continue to monitor the RX FIFO and empty it as needed.
a. The FIFO level can be monitored synchronously via the RX FIFO status/interrupt flags, or asynchronously
by setting I2Cn_RX_CTRL0.rxth and enabling the I2Cn_INT_FL0.rxthi interrupt.
b. If the RX FIFO ever fills up during the transaction, then hardware will set I2Cn_INT_FL1.rxofi and then
either:
i. if I2Cn_CTRL0.scl_strd = 0, start clock stretching and wait for software to read from the RX FIFO,
or,
ii. if I2Cn_CTRL0.scl_strd =1, respond to the master with a NACK and the last byte is discarded.
6. The master ends the transaction by sending a RESTART or STOP. Once this happens the I2Cn_INT_FL0.donei
interrupt flag is set, and software can stop monitoring the RX FIFO.
7. Once a slave starts receiving into its RX_FIFO, detection of out of sequence STOP, START or RESTART condition will
release the I
2
C bus to the Idle state and hardware will set I2Cn_INT_FL0.strteri or I2Cn_INT_FL0.stoperi to 1.
If software has not emptied the data in the RX FIFO from the previous transaction by the time that a master addresses it for
another write (i.e. receive) transaction, then the controller will not participate in the transaction, and no additional data will
be written into the FIFO. Although a NACK will be sent to the master, software can control whether the NACK is sent with
the initial address match, or if instead it is sent at the end of the first data byte. Setting I2Cn_RX_CTRL0.dnr to 1 chooses the
former, while setting I2Cn_RX_CTRL0.dnr to 0 chooses the latter.
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