MAX32665-MAX32668 User Guide
Maxim Integrated Page 286 of 457
To use slave transmit preload mode:
1. With I2Cn_CTRL0.i2cen = 0, initialize all relevant registers, including specifically for this mode I2Cn_CTRL0.scl_strd =
1, I2Cn_TX_CTRL0[5:2] = 0xF and I2Cn_TX_CTRL0.txpreld=1.
2. SW sets I2Cn_CTRL0.i2cen = 1.
a. Even though the controller is enabled, at this point it will not ACK an address match with R/W=1 until SW sets
I2Cn_TX_CTRL1.txrdy =1.
3. SW prepares for the transmit operation by loading data into the transmit FIFO, enabling DMA, setting
I2Cn_TX_CTRL0.txth and setting I2Cn_INT_EN0.txthie interrupt, etc.
a. If clock stretching is disabled, then an empty TX FIFO during the transmit operation will cause a TX underrun
error. Therefore, firmware should take any necessary steps to avoid an underrun prior to setting
I2Cn_TX_CTRL1.txrdy =1.
b. If clock stretching is enabled, then an empty TX FIFO will not cause a TX underrun error. However, it is
recommended to follow the same preparation steps in order to minimize the amount of time spent clock
stretching, which will let the transaction complete as quickly as possible.
4. Once SW has prepared for the transmit operation, it sets I2Cn_TX_CTRL1.txrdy =1.
a. The controller is now fully enabled and will respond with an ACK to an address match.
b. HW will set I2Cn_INT_FL0.ami once an address match has occurred. I2Cn_INT_FL0.txloi. will NOT be set and
will remain 0.
5. SW waits for I2Cn_INT_FL0.ami =1, either via polling the interrupt flag or setting I2Cn_INT_EN0.amie to interrupt
the CPU.
6. After seeing I2Cn_INT_FL0.ami =1, SW reads I2Cn_CTRL0.read to determine whether the transaction is a transmit
(read=1) or receive (read=0) operation. In this case we assume I2Cn_CTRL0.read, indicating transmit.
a. At this point, HW will begin sending out the data that was preloaded into the TX FIFO.
b. Once the first data byte is sent, HW will also automatically clear I2Cn_TX_CTRL1.txrdy to 0.
7. While the master keeps requesting data and sending ACKs, I2Cn_INT_FL0.donei will remain 0 and SW should
continue to monitor the TX FIFO and refill it as needed.
a. The FIFO level can be monitored synchronously via the TX FIFO status/interrupt flags, or asynchronously by
setting I2Cn_TX_CTRL0.txth and setting I2Cn_INT_EN0.txthie interrupt.
b. If clock stretching is disabled and the TX FIFO ever empties during the transaction, the HW will set
I2Cn_INT_FL1.txufi=1 and send 0xFF for all following data bytes requested by the master.
8. The master ends the transaction by sending a NACK. Once this happens the I2Cn_INT_FL0.donei interrupt flag is
set.
a. If the TX FIFO goes empty at the same time that the master indicates the transaction is complete by sending a
NACK, this is not considered an underrun event, and the I2Cn_INT_FL1.txufi flag will remain 0.
9. The transaction is complete, SW should "clean up", which should include clearing I2Cn_INT_FL0.donei. We return
to step 3 and prepare for the next transaction.
a. If SW needs to know how many data bytes were transmitted to the master, it should check the TX FIFO level as
soon as SW sees I2Cn_INT_FL0.donei = 1 and use that to determine how many data bytes were successfully
sent.
b. By default, any data remaining in the TX FIFO will NOT be discarded, and instead will be reused for the next
transmit operation.
c. If this is not desired, SW can flush the TX FIFO. The safest way to do this is by clearing and then re-setting
i2cen. This will flush both the TX and RX FIFOs.
Once a slave starts transmitting out of its I2Cn_FIFO, detection of out of sequence STOP, START or RESTART condition will
terminate the current transaction. When a transaction is terminated in such manner, I2Cn_INT_FL0.strteri or
I2Cn_INT_FL0.stoperi will be set to 1.
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