MAX32665-MAX32668 User Guide
Maxim Integrated Page 268 of 457
Transmit FIFO Threshold Level Interrupt Enable
Enables the Transmit FIFO threshold level interrupt. This interrupt occurs when the
number of entries in the Transmit FIFO is equal or less than the value set in
UARTn_CTRL1.tx_fifo_lvl.
0: Disabled.
1: Enabled.
Transmit FIFO Almost Empty Interrupt Enable
This interrupt occurs when there is one byte remaining in the Transmit FIFO.
0: Disabled.
1: Enabled.
Receive FIFO Threshold Level Interrupt Enable
0: Disabled
1: Enabled
Note: See Table 12-1: UART Interrupt Conditions for description.
Receive FIFO Overrun Interrupt Enable
0: Disabled.
1: Enabled.
Note: See Table 12-1: UART Interrupt Conditions for description.
CTS State Change Interrupt Enable
Enable the CTS level change interrupt event. This is often referred to as Modem Status
Interrupt.
0: Disabled.
1: Enabled.
Receive Parity Error Interrupt Enable
0: Disabled.
1: Enabled.
Receive Frame Error Interrupt Enable
0: Disabled.
1: Enabled.
Table 12-8: UART Interrupt Flags Register
Reserved for Future Use
Do not modify this field.
BREAK End Interrupt Flag
When the UART receives a series of BREAK frames, this flag is set when the last BREAK
frame is received. Write 1 to clear this field.
0: Last BREAK condition has not occurred.
1: Last BREAK condition has occurred.
Note: See Table 12-1: UART Interrupt Conditions for description.
Receive Frame Timeout Interrupt Flag
This field is set when a receive frame timeout occurs. Write 1 to clear this field.
0: Receive frame timeout has not occurred.
1: A receive frame timeout was detected by the UART.