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Maxim Integrated MAX32665 - Registers; Register Details; Table 18-4. RTC Register Summary; Table 18-5. RTC Seconds Counter Register

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 376 of 457
Complete the following steps to perform an RTC calibration:
1. If not already, software configures and enables one of the compensated calibration frequencies as described in
section Square Wave Output.
2. Measure the frequency on the square wave output pin and compute the deviation from an accurate reference
clock.
3. Software clears RTC_CTRL.ready to 0.
4. Wait for RTC_CTRL.ready = 1 by:
5. Software sets RTC_CTRL.ready_int_en to 1 to generate an interrupt when RTC_CTRL.ready = 1, or
6. Software polls RTC_CTRL.ready until the field = 1.
7. Software polls until RTC_CTRL.busy=0 to make sure any previous operations are complete
8. Software sets RTC_CTRL.write_en to 1 to allow access to RTC_TRIM.
9. Software writes to RTC_TRIMregister as desired to correct for measured inaccuracy.
10. Hardware clears RTC_CTRL.busy =0.
11. Software clears RTC_CTRL.write_en to 0.
12. Repeat the process as needed until the desired accuracy is achieved
18.6 Registers
Refer to Table 3-1: APB Peripheral Base Address Map for this peripheral/module's base address. If multiple instances are
provided, each will have a unique base address. All fields in this peripheral are reset on POR only; refer to the field
description for details.
Table 18-4. RTC Register Summary
Register
Offset
Description
RTC_SEC
[0x0000]
RTC Seconds Counter Register
RTC_SSEC
[0x0004]
RTC Sub-Second Counter Register
RTC_TODA
[0x0008]
RTC Time-of-Day Alarm Register
RTC_SSECA
[0x000C]
RTC Sub-Second Alarm Register
RTC_CTRL
[0x0010]
RTC Control Register
RTC_TRIM
[0x0014]
RTC 32KHz Oscillator Digital Trim Register
RTC_OSCCTRL
[0x0018]
RTC 32KHz Oscillator Control Register
18.7 Register Details
Table 18-5. RTC Seconds Counter Register
RTC Seconds Counter
RTC_SEC
Bits
Field
Access
Reset
Description
31:0
sec
R/W
0
Seconds Counter
This register is a binary count of seconds.
Table 18-6. RTC Sub-Second Counter Register (12-bit)
RTC Sub-Seconds Counter
RTC_SSEC
Bits
Field
Access
Reset
Description
31:12
-
R/W
0
Reserved for Future Use
Do not modify this field.
11:0
ssec
R/W
0
Sub-Seconds Counter (12-bit)
RTC_SEC increments when this field rolls from 0x0FFF to 0x0000

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