Maxim Integrated MAX32665 - Table 8-61: SDHC Response 7 Register; Table 8-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention; Table 8-63: Kind of SD Card Response Mapping to SDHC Response Registers; Table 8-64: SDHC Buffer Data Port Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 193 of 457
Table 8-61: SDHC Response 7 Register
Response 7 Register
SDHC_RESP_7
[0x001E]
Bits
Name
Access
Reset
Description
15:0
cmd_resp
RO
0
Response Register 7
Response 7 to Response 0 registers are referenced as a contiguous, single register in
the SD Host Controller Spec V3.0. Table 8-62 shows the mapping from the Response
Registers to the SD Host Controller Standard Specification REP[127:0] notation for the
MAX32665—MAX32668. Table 8-63 shows the SD types of response mapped to the
MAX32665—MAX32668 Response registers.
Table 8-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention
Register
Register Name
Register Offset
SDHC REP[] Bit Mapping
SDHC_RESP_0
Response 0
0x10
REP[15:0]
SDHC_RESP_1
Response 1
0x12
REP[31:16]
SDHC_RESP_2
Response 2
0x14
REP[47:32]
SDHC_RESP_3
Response 3
0x16
REP[63:48]
SDHC_RESP_4
Response 4
0x18
REP[79:64]
SDHC_RESP_5
Response 5
0x1A
REP[95:80]
SDHC_RESP_6
Response 6
0x1C
REP[111:96]
SDHC_RESP_7
Response 7
0x1E
REP[127:112]
Table 8-63: Kind of SD Card Response Mapping to SDHC Response Registers
Kind of Response
Meaning of Response
REP[] Specification
Mapping
SDHC Response
Register MSW
SDHC Response
Register LSW
R1, R1b (normal response)
Card Status
REP[31:0]
SDHC_RESP_1
SDHC_RESP_0
R1b (Auto CMD12 response)
Card Status for Auto CMD12
REP[127:96]
SDHC_RESP_7
SDHC_RESP_6
R1 (Auto CMD23 response)
Card Status for Auto CMD23
REP[127:96]
SDHC_RESP_7
SDHC_RESP_6
R2 (CID, CSD register)
CID or CSD reg. incl.
REP [119:0]
SDHC_RESP_7
SDHC_RESP_0
R3 (OCR register)
OCR register for memory
REP [31:0]
SDHC_RESP_1
SDHC_RESP_0
R4 (OCR register)
OCR register for I/O, etc
REP [31:0]
SDHC_RESP_1
SDHC_RESP_0
R5, R5b
SDIO response
REP [31:0]
SDHC_RESP_1
SDHC_RESP_0
R6 (Published RCA response)
Newly published RCA[31:16], etc
REP [31:0]
SDHC_RESP_1
SDHC_RESP_0
Table 8-64: SDHC Buffer Data Port Register
Buffer Data Port Register
SDHC_BUFFER
[0x0020]
Bits
Name
Access
Reset
Description
31:0
data
R/W
0
Buffer Data
Pointer to the SDHC internal data buffer.
Table 8-65: SDHC Present State Register
Present State Register
SDHC_PRESENT
[0x0024]
Bits
Name
Access
Reset
Description
31:25
-
RO
0
Reserved for Future Use
Do not modify this field.
24
cmd_signal_level
RO
0
CMD Line Signal Level
Indicates the CMD line level for error recovery and debugging.