Maxim Integrated MAX32665 - Table 14-11: Qspin Slave Select Timing Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 318 of 457
QSPIn Control 2 Register
QSPIn_CTRL2
[0x000C]
Bits
Name
Access
Reset
Description
1
clkpol
R/W
0
Clock Polarity
This field controls the SCK polarity. The default clock polarity is for SPI Mode 0
and Mode 1 operation and is active high. Invert the SCK polarity for SPI Mode 2
and Mode 3 operation.
0: Standard SCK for use in SPI Mode 0 and Mode 1
1: Inverted SCK for use in SPI Mode 2 and Mode 3
0
phase
R/W
0
Clock Phase
0: Data sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
1: Data sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
Table 14-11: QSPIn Slave Select Timing Register
QSPIn Slave Select Timing Register
QSPIn_SS_TIME
[0x0010]
Bits
Name
Access
Reset
Description
31:24
-
R/W
0
Reserved for Future Use
Do not modify this field.
23:16
inact
R/W
0
Inactive Stretch
This field controls the number of system clocks the bus is inactive between the
end of a transaction (Slave Select inactive) and the start of the next transaction
(Slave Select active).
0: 256
1: 1
2: 2
3:3
…
…
254: 254
255: 255
15:8
post
R/W
0
Slave Select Hold Post Last SCK
Number of system clock cycles that SS remains active after the last SCK edge.
0: 256
1: 1
2: 2
3:3
…
…
254: 254
255: 255
7:0
pre
R/W
0
Slave Select Delay to First SCK
Set the number of system clock cycles the Slave Select is held active prior to the
first SCK edge.
0: 256
1: 1
2: 2
3:3
…
…
254: 254
255: 255