MAX32665-MAX32668 User Guide
Maxim Integrated Page 304 of 457
Clock High Time
In Master Mode, this configures the SCL high time.
In both Master and Slave Mode, this also configures the time SCL is held low after
new data is loaded from the TX FIFO or after firmware clears irxmi during
Interactive Receive Mode.
Note: 0 is not a valid setting for this field.
Table 13-21: I
2
C Hs-Mode Clock Control Register
I
2
C Hs-Mode Clock Control
Reserved for Future Use
Do not modify this field.
Hs-Mode Clock High Time
This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is
held high after data is output on SDA.
Note: See section 13.4.4 SCL Clock Generation for Hs-mode for details on the
requirements for the Hs-mode clock high and low times.
Hs-Mode Clock Low Time
This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is
held low after data is output on SDA.
Note: See section 13.4.4 SCL Clock Generation for Hs-mode for details on the
requirements for the Hs-mode clock high and low times.
Table 13-22: I
2
C Timeout Register
Bus Error SCL Timeout Period
Set this value to the number of I
2
C clock cycles desired to cause a bus timeout error.
The peripheral timeout timer starts when it pulls SCL low. After the peripheral
releases the line, if the line is not pulled high prior to the timeout number of I
2
C
clock cycles, a bus error condition is set (I2Cn_INT_FL0.toeri = 1) and the peripheral
releases the SCL and SDA lines
0: Timeout disabled.
All other values result in a timeout calculation of:
Note: The timeout counter monitors the I2Cn peripheral’s driving of the SCL pin, not
an external I
2
C device driving the SCL pin.
Table 13-23: I
2
C DMA Register
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