Maxim Integrated MAX32665 - Table 8-78: SDHC Error Interrupt Status Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 208 of 457
Normal Interrupt Status Enable Register
SDHC_INT_EN
[0x0034]
Bits
Name
Access
Reset
Description
5
buffer_rd
R/W
0
Buffer Read Ready Status Enable
Set to enable Buffer Read Ready status.
1: Enabled
0: Disabled
4
buffer_wr
R/W
0
Buffer Write Ready Status Enable
Set to enable Buffer Write Ready status.
1: Enabled
0: Disabled
3
dma
R/W
0
DMA Interrupt Status Enable
Set to enable DMA status.
1: Enabled
0: Disabled
2
blk_gap
R/W
0
Block Gap Event Status Enable
Set to enable Block Gap status.
1: Enabled
0: Disabled
1
trans_comp
R/W
0
Transfer Complete Status Enable
Set to enable Transfer Complete status.
1: Enabled
0: Disabled
0
cmd_comp
R/W
0
Command Complete Status Enable
Set to enable Command Complete status.
1: Enabled
0: Disabled
Table 8-78: SDHC Error Interrupt Status Enable Register
Error Interrupt Status Enable Register
SDHC_ER_INT_EN
[0x0036]
Bits
Name
Access
Reset
Description
15:13
-
R/W
0
Reserved for Future Use
Do not modify this field.
12
vendor
R/W
0
Target Response Error/Host Error Status Enable
Set to enable Target Response/Host Error status interrupts.
1: Enabled
0: Disabled
11
-
R/W
0
Reserved for Future Use
Do not modify this field.
10
tuning
R/W
0
Tuning Error Status Interrupt Enable
1: Enabled
0: Disabled
9
adma
R/W
0
ADMA Error Status Interrupt Enable
1: Enabled
0: Disabled