Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 85 of 457
Low Power VDD Power Down
PWRSEQ_LPVDDPD
[0x0044]
Bits
Field
Access
Reset
Description
10
vdd4pd
R/W
0
Reserved
Reserved. Do not modify this field.
9
vdd3pd
R/W
0
Reserved
Reserved. Do not modify this field.
8
vdd2pd
R/W
0
Reserved
Reserved. Do not modify this field.
7:2
-
R/W
-
Reserved
Reserved. Do not modify this field.
1
vregodpd
R/W
0
VREGO_D Regulator ACTIVE Mode Power Down
0: Regulator enabled in ACTIVE mode
1: Regulator enabled in ACTIVE mode
0
vregobpd
R/W
0
VREGO_B Regulator BACKUP Mode Power Down
0: Regulator enabled in BACKUP mode
1: Regulator automatically disabled when entering BACKUP mode
Table 4-51: BACKUP Return Vector Register
BACKUP Return Vector
PWRSEQ_BURETVEC
[0x0048]
Bits
Field
Access
Reset
Description
31:0
gpr0
R/W
0
BACKUP Return Vector
This register is used as a jump address when waking from BACKUP mode.
Table 4-52: BACKUP AoD Register
BACKUP AoD
PWRSEQ_BUAOD
[0x004C]
Bits
Field
Access
Reset
Description
31:0
gpr1
R/W
0
General Purpose Register 0
This register can be used for storage as it is preserved in the AoD domain from
BACKUP mode.
4.16 Global Control Registers (GCR)
See Table 3-1: APB Peripheral Base Address Map for the General Control Register’s Peripheral Address.
Note: The General Control Registers are only reset on a System Reset or Power-On Reset. A Soft Reset or Peripheral Reset
does not affect these registers.
Table 4-53: Global Control Register Summary
Offset
Register
Description
[0x0000]
GCR_SCON
System Control Register
[0x0004]
GCR_RST0
Reset Register 0
[0x0008]
GCR_CLK_CTRL
Clock Control Register
[0x000C]
GCR_PMR
Power Management Register
[0x0018]
GCR_PCLK_DIV
Peripheral Clocks Divisor
[0x0024]
GCR_PCLK_DIS0
Peripheral Clocks Disable 0
[0x0028]
GCR_MEM_CLK
Memory Clock Control
[0x002C]
GCR_MEM_ZERO
Memory Zeroize Register

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English