Maxim Integrated MAX32665 - Table 3-6: Error Correction Coding (ECC) Interrupt Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 47 of 457
Correctable Error Detected
GCR_ECC_CED
[0x0068]
Bits
Field
Access
Reset
Description
1
sysram1ecc_ced
R/W1C
0
ECC Sysram1 Correctable Error Detected
Indicates a single bit correctable error in the Sysram 1 block. Write to 1 to clear.
0: No single bit error detected
1: Correctable
0
sysram0ecc_ced
R/W1C
0
ECC Sysram0 Correctable Error Detected
Indicates a single bit correctable error in the Sysram 0 block. Write to 1 to clear.
0: No single bit error detected
1: Correctable
Table 3-6: Error Correction Coding (ECC) Interrupt Enable Register
Error Correction Coding Interrupt Enable
GCR_ECC_IRQEN
[0x006C]
Bits
Field
Access
Reset
Description
31:13
-
RO
0
Reserved for Future Use
Do not modify this field.
12
fl1eccirqen
R/W
0
ECC Flash1 Interrupt Enable
When set, indicates that ECC is enabled for the block and interrupts occur upon
a detected error.
0: Disabled
1: Enabled
11
fl0eccirqen
R/W
0
ECC Flash0 Interrupt Enable
When set, indicates that ECC is enabled for the block and interrupts occur upon
a detected error.
0: Disabled
1: Enabled
10
icspixfeccirqen
R/W
0
ECC SPIXF Instruction Cache Interrupt Enable
When set, indicates that ECC is enabled for the block and interrupts occur upon
a detected error.
0: Disabled
1: Enabled
9
ic1eccirqen
R/W
0
ECC Instruction Cache 1 Interrupt Enable
When set, indicates that ECC is enabled for the block and interrupts occur upon
a detected error.
0: Disabled
1: Enabled
8
ic0eccirqen
R/W
0
ECC Instruction Cache 0 Interrupt Enable
When set, indicates that ECC is enabled for the block and interrupts occur upon
a detected error.
0: Disabled
1: Enabled
7:6
-
RO
0
Reserved for Future Use
Do not modify this field.
5
sysram5irqen
R/W
0
ECC Sysram5 Interrupt Enable
When set, indicates that the interrupt is enabled for occurrence upon a
detected error in the Sysram5 block if GCR_ECC_EN.sysram5en is set.
0: Disabled
1: Enabled