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Maxim Integrated MAX32665 - SDHC Registers; Table 8-45: SDHC Register Offsets, Names and Descriptions

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 185 of 457
Register
SDMA Command
ADMA Command
CPU Data Transfer
Non-DAT (No Data) Transfer
Argument 2
SDHC_SDMA
Yes
Yes
Yes
No (Protected)
Command
SDHC_CMD
Yes
Yes
Yes
Yes
8.5.5 SDHC Registers
See Table 3-1: APB Peripheral Base Address Map for the SDHC Peripheral Base Address
Table 8-45: SDHC Register Offsets, Names and Descriptions
Offset
Register Name
Description
[0x0000]
SDHC_SDMA
SDMA System Address / Argument 2
[0x0004]
SDHC_BLK_SIZE
Block Size register
[0x0006]
SDHC_BLK_CNT
Block Count register
[0x0008]
SDHC_ARG_1
Argument 1 register
[0x000C]
SDHC_TRANS
Transfer Mode register
[0x000E]
SDHC_CMD
Command register
[0x0010]
SDHC_RESP_0
Response register 0
[0x0012]
SDHC_RESP_1
Response register 1
[0x0014]
SDHC_RESP_2
Response register 2
[0x0016]
SDHC_RESP_3
Response register 3
[0x0018]
SDHC_RESP_4
Response register 4
[0x001A]
SDHC_RESP_5
Response register 5
[0x001C]
SDHC_RESP_6
Response register 6
[0x001E]
SDHC_RESP_7
Response register 7
[0x0020]
SDHC_BUFFER
Buffer Data Port register
[0x0024]
SDHC_PRESENT
Present State register
[0x0028]
SDHC_HOST_CN_1
Host Control 1 register
[0x0029]
SDHC_PWR
Power Control register
[0x002A]
SDHC_BLK_GAP
Block Gap Control register
[0x002B]
SDHC_WAKEUP
Wakeup Control register
[0x002C]
SDHC_CLK_CN
Clock Control register
[0x002E]
SDHC_TO
Timeout Control register
[0x002F]
SDHC_SW_RESET
Software Reset register
[0x0030]
SDHC_INT_STAT
Normal Interrupt Status register
[0x0032]
SDHC_ER_INT_STAT
Error Interrupt Status register
[0x0034]
SDHC_INT_EN
Normal Interrupt Status Enable register
[0x0036]
SDHC_ER_INT_EN
Error Interrupt Status Enable register
[0x0038]
SDHC_INT_SIGNAL
Normal Interrupt Signal Enable register
[0x003A]
SDHC_ER_INT_SIGNAL
Error Interrupt Signal Enable register
[0x003C]
SDHC_AUTO_CMD_ER
Auto CMD Error Status register
[0x003E]
SDHC_HOST_CN_2
Host Control 2 register
[0x0040]
SDHC_CFG_0
Capabilities register 0
[0x0044]
SDHC_CFG_1
Capabilities register 1
[0x0048]
SDHC_MAX_CURR_CFG
Maximum Current Capabilities register

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