Maxim Integrated MAX32665 - Table 8-69: SDHC Wakeup Control Register; Table 8-70: SDHC Clock Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 199 of 457
Table 8-69: SDHC Wakeup Control Register
Wakeup Control Register
SDHC_WAKEUP
[0x002B]
Bits
Name
Access
Reset
Description
7:3
-
R/W
0
Reserved for Future Use
Do not modify this field.
2
card_rem
R/W
0
Wakeup Event Enable on SD Card Removal
Enable wakeup event interrupt when the SDHC_INT_STAT.card_removal flag
occurs.
1: Enable Interrupt
0: Disable Interrupt
1
card_ins
R/W
0
Wakeup Event Enable on SD Card Insertion
Enable wakeup event interrupt when the SDHC_INT_STAT.card_inserted flag
occurs.
1: Enable Interrupt
0: Disable Interrupt
0
card_int
R/W
0
Wakeup Event Enable On Card Interrupt
Enable wakeup event interrupt when the SDHC_INT_STAT.card_intr flag occurs.
Table 8-70: SDHC Clock Control Register
Clock Control Register
SDHC_CLK_CN
[0x002C]
Bits
Name
Access
Reset
Description
15:8
sdclk_freq_sel
R/W
0
SDCLK Frequency Select
Selects the SD Clock Frequency output on the SDHC_CLK pin.
The SD Clock Frequency Select is a total of 10bits. The divisors shown below consist
of the upper_sdclk_freq_sel bits as bits 9:8, and the sdclk_freq_sel bits as bits 7:0
of the divisor.
upper_sdclk_freq_sel
sdclk_freq_sel
SDCLK
Divisor (N)
0b11
0b11111111
1023
0b11
0b00000000
768
…
…
…
0b10
0b01010101
597
….
….
….
….
….
N
….
….
….
0b00
0b00000010
2
0b00
0b00000001
1
0b00
0b00000000
0 (MAX)
Setting upper_sdclk_freq_sel and sdclk_freq_sel to 0 results in the maximum
SDCLK frequency of f
SDHC_CLK_FRQ
. All other settings for upper_sdclk_freq_sel and
sdclk_freq_sel follow the equation below:
SDHCCLK 
f
SDHCCLKFRQ
󰇛
2  N
󰇜

Note: The SD Clock Enable must be disabled (SDHC_CLK_CN.sd_clk_en = 0) prior to
modification of this field.