Maxim Integrated MAX32665 - Page 200

MAX32665-MAX32668 User Guide
Maxim Integrated Page 200 of 457
Clock Control Register
SDHC_CLK_CN
[0x002C]
Bits
Name
Access
Reset
Description
7:6
upper_sdclk_freq_sel
R/W
0
Upper Bits of SDCLK Frequency Select
Bits 9 and 8 of the 10-bit SDCLK frequency select. See the
SDHC_CLK_CN.sdclk_freq_sel field for details about the clock select calculation.
Note: The SD Clock Enable must be disabled (SDHC_CLK_CN.sd_clk_en = 0) prior to
modification of this field.
5
clk_gen_sel
RO
0
Clock Generator Select
Reads 0 indicating Divided Clock mode only for SD Clock Frequency generation.
0: Divided clock mode
4:3
-
RO
0
Reserved for Future Use
Do not modify this field.
2
sd_clk_en
R/W
0
SD Clock Enable
Enable/disable SD Clock generation.
1: Enable the SD Clock and output on the SDHC_CLK pin.
0: SD Clock is disabled.
Note: This bit is cleared by the SDHC if the card-inserted field in the Present State
register is cleared.
Note: The internal_clk_en bit must be set to 1, and the internal_clk_stable bit must
read 1 prior to setting this bit to 1.
1
internal_clk_stable
RO
0
Internal Clock Stable
This bit is set to 1 when the internal clock is stable.
Note: The internal clock must be enabled (SDHC_CLK_CN.internal_clk_en = 1)
before this field is used.
0
internal_clk_en
R/W
0
Internal Clock Enable
Enable the internal clock.
Note: This bit must be set, and the internal_clk_stable bit must read 1 prior to
setting the SD Clock Enable (SDHC_CLK_CN.sd_clk_en) bit.
Note: This bit is set to 0 by the SDHC if waiting for a wakeup interrupt.