MAX32665-MAX32668 User Guide
Maxim Integrated Page 39 of 457
3.2.5 External Device Space
The external device space area of memory is intended for use in mapping off-chip device control functions onto the AHB
bus. This memory space is defined from byte address range 0xA000 0000 to 0xDFFF FFFF (1GB maximum). The MAX32665—
MAX32668 does not implement this memory area.
3.2.6 System Area (Private Peripheral Bus)
The system area (private peripheral bus) memory space contains register areas for functions that are only accessible by the
Arm core itself (and the Arm debugger, in certain instances). It is defined from byte address range 0xE000 0000 to
0xE00F FFFF. This APB bus is restricted and can only be accessed by the Arm core and core-internal functions. It cannot be
accessed by other modules which implement AHB memory masters, such as the SD/SDIO/SDHC/MMC interface.
In addition to being restricted to the core, application code is only allowed to access this area when running in the
privileged execution mode (as opposed to the standard user thread execution mode). This helps ensure that critical system
settings controlled in this area are not altered inadvertently or by errant code that should not have access to this area.
Core functions controlled by registers mapped to this area include the SysTick timer, debug and tracing functions, the NVIC
(interrupt handler) controller, and the Flash Breakpoint controller.
3.2.7 System Area (Vendor Defined)
The system area (vendor defined) memory space is reserved for vendor (system integrator) specific functions that are not
handled by another memory area. It is defined from byte address range 0xE010 0000 to 0xFFFF FFFF. The MAX32665—
MAX32668 does not implement this memory region.
3.3 Device Memory Instances
This section details physical memory instances on the MAX32665—MAX32668 (including internal flash memory and SRAM
instances) that are accessible as standalone memory regions using either the AHB or APB bus matrix. Memory areas which
are only accessible via FIFO interfaces, or memory areas consisting of only a few registers for a specific peripheral, are not
covered here.
3.3.1 Main Program Flash Memory
The main program flash memory is 1MB in size (two banks of 512KB) and consists of 128 logical pages of 8,192 Bytes per
page.
3.3.2 Cache Memories
3.3.2.1 Instruction Cache Controller 0 (ICC0)
The internal flash memory instruction cache is 16,384 Bytes in size and is used to cache instructions fetched using the
I-Code bus, including instructions fetched from the internal flash memory. This instruction cache controller is referred to as
ICC0 throughout this document.
3.3.2.2 Instruction Cache Controller 1 (ICC1)
The SPIXF instruction cache, managed by ICC1, is also 16,384 Bytes and is used to cache instructions fetched from an
external SPI memory device. ICC1 is only available if the SPIXF controller is enabled.
Note: The instruction caches, ICC0 and ICC1, are used for instruction fetches only. Data fetches (including code literal values)
from the internal flash memory or external SPIXF memory do not use the instruction cache.
To Next Page
Loading...
Need help?
General