MAX32665-MAX32668 User Guide
Maxim Integrated Page 142 of 457
8. External Memory
8.1 Overview
External memory can be accessed via multiple interfaces. There are three external memory interfaces, two of which are
backed by 16KB of cache:
• SPI Execute-in-Place FLASH (SPIXF)
16KB dedicated cache
• SPI Execute-in-Place RAM (SPIXR)
16KB dedicated cache
• SD/SDIO/SDHC/MMC
8.2 SPI Execute-in-Place Flash (SPIXF)
The SPIXF provides the following features:
• Up to 48MHz operation in mode 0 and 3
• Sigle slave select
• Four wire mode for single-bit slave device communication
• Dual and Quad I/O supported
• Programmable SCK frequency and duty cycle
• SS assertion and de-assertion timing with respect to the leading and trailing SCK edge
• Configurable command, address, dummy, and data fields to support a variety of SPI flashes
The SPIXF allows the CPU to transparently execute instructions stored in an external SPI flash. Instructions fetched using the
SPIXF are cached just like instructions fetched from internal program memory. You can also use the SPIXF to access large
amounts of external static data that would otherwise reside in internal data memory. This device provides support for a
wide variety of external SPI flash memory devices.
Prior to using the SPI flash device, you must configure the SPIXF interface.
To prevent disclosure of intellectual property, code and data can optionally be stored in external flash in an encrypted form
using the SPIXF. Generation of the encrypted data can be done via user firmware or with the cryptographic accelerator. The
SPIXF can transparently decrypt this information in real time using Memory Decryption Integrity Unit (MDOU) with the AES-
128 algorithm in ECB mode.
The SPIXF consists of the SPIXF Master and SPIXF Master Controller as shown in the diagram below. The SPIXF Master
transparently reads the external SPI flash device while the SPIXF Master Controller is used to manually write data to the
external SPI flash and to configure the SPI external flash device registers.
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