MAX32665-MAX32668 User Guide
Maxim Integrated Page 283 of 457
Also, in a multi-master environment, application firmware does not need to wait for the bus to become free before
attempting to start a transaction (writing 1 to I2Cn_MSTR_MODE.start). If the bus is free when I2Cn_MSTR_MODE.start is
set to 1, the transaction begins immediately. If instead the bus is busy, then the peripheral will:
1. Wait for the other master to complete the transaction(s) by sending a STOP,
2. Count out the bus free time using
(see Equation 13-2), and then
3. Send a START condition and begin transmitting the slave address byte(s) in the TX FIFO, followed by the rest of the
transfer.
The I
2
C master peripheral is compliant with all bus arbitration and clock synchronization requirements of the I
2
C
specification; this operation is automatic, and no additional programming is required.
13.4.7 I
2
C Slave Mode Operation
When in slave mode, the I2Cn peripheral operates as a slave device on the I
2
C bus and responds to an external master’s
requests to transmit or receive data. To configure the I2Cn peripheral as a slave, write the I2Cn_CTRL0.mst bit to zero. The
I2Cn clock is driven by the master on the bus, so the SCL device pin will be driven by the external master and
I2Cn_STAT.ckmd remains a zero. The desired slave address must be set by writing to the I2Cn_SLV_ADDR.sla register.
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