MAX32665-MAX32668 User Guide
Maxim Integrated Page 282 of 457
13.4.6.2 I
2
C Master Mode Transmitter Operation
When in Master Mode, initiating a Master Transmitter operation begins with the following sequence:
1. Write the I
2
C Slave Address Byte to the I2Cn_FIFO register with the R/W bit set to 0
2. Write the desired data bytes to the I2Cn_FIFO register, up to the size of the TX FIFO. (e.g. If the TX FIFO size is 8
bytes, firmware may write one address byte and seven data bytes prior to starting the transaction.)
3. Send a START condition by setting I2Cn_MSTR_MODE.start = 1
4. The controller transmits the slave address byte written to the I2Cn_FIFO register.
5. The I
2
C controller receives an ACK from the slave and the controller sets the address ACK interrupt flag
(I2Cn_INT_FL0.adracki = 1).
6. The I2Cn_FIFO register data bytes are transmitted on the SDA line.
a. The I
2
C controller receives an ACK from the slave after each data byte
b. As the transfer proceeds, firmware should refill the TX FIFO by writing to the I2Cn_FIFO register as needed.
c. If the TX FIFO goes empty during this process, the controller will pause at the beginning of the byte and wait for
firmware to either write more data or instruct the controller to send a RESTART or STOP condition.
7. Once firmware has written all the desired bytes to the I2Cn_FIFO register, firmware should set either
I2Cn_MSTR_MODE.restart or I2Cn_MSTR_MODE.stop.
8. Once the controller sends all the remaining bytes and empties the TX FIFO, it will set I2Cn_INT_FL0.donei and
proceed to send out either a RESTART condition, if I2Cn_MSTR_MODE.restart was set, or a STOP condition, if
I2Cn_MSTR_MODE.stop was set.
13.4.6.3 I
2
C Multi-Master Operation
The I
2
C protocol supports multiple masters on the same bus. When the bus is free, it is possible that two (or more) masters
might try to initiate communication at the same time. This is a valid bus condition. If this occurs and the two masters want
to transmit different data and/or address different slaves, only one master can remain in master mode and complete its
transaction. The other master must back off transmission and wait until the bus is idle. This process by which the winning
master is determined is called bus arbitration.
To determine which master wins the arbitration, for each address or data bit, the master compares the data being
transmitted on SDA to the value observed on SDA. If a master attempts to transmit a 1 on SDA (that is, the master lets SDA
float) but senses a 0 instead, then that master loses arbitration, and the other master that sent a zero continues with the
transaction. The losing master cedes the bus by switching off its SDA and SCL drivers.
Note that this arbitration scheme works with any number of bus masters: if more than two masters begin transmitting
simultaneously, the arbitration continues as each master cedes the bus until only one master remains transmitting. Data is
not corrupted because as soon as each master realizes it has lost arbitration, it stops transmitting on SDA, leaving the
following data bits sent on SDA intact.
If the I
2
C master peripheral detects it has lost arbitration, it stops generating SCL; sets I2Cn_INT_FL0.areri; sets
I2Cn_INT_FL0.txloi, flushing any remaining data in the TX FIFO; and clears I2Cn_MSTR_MODE.start,
I2Cn_MSTR_MODE.restart, and I2Cn_MSTR_MODE.stop to 0. So long as the peripheral is not itself addressed by the
winning master, the I
2
C peripheral stays in master mode (I2Cn_CTRL0.mst = 1). If at any time another master addresses this
peripheral using the address programmed in I2Cn_SLV_ADDR.sla, then the I
2
C peripheral clears I2Cn_CTRL0.mst to 0 and
begins responding as a slave. This can even occur during the same address transmission during which the peripheral lost
arbitration.
Note: Arbitration loss is considered an error condition, and like the other error conditions will set txloi. Therefore, after an
arbitration loss, firmware will need to clear I2Cn_INT_FL0.txloi and reload the TX FIFO.
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