Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 422 of 457
Table 21-24: USBHS OUT Endpoint Upper Control Status Register
USBHS OUT Endpoint Upper Control Status Register
USBHS_OUTCSRU
[0x0017]
Bits
Name
Access
Reset
Description
7
autoclear
R/W
0
Auto Clear outpktrdy
0: USBHS_OUTCSRL.outpktrdy must be cleared by firmware.
1: USBHS_OUTCSRL.outpktrdy is automatically cleared when data that is of the
maximum packet size specified in the USBHS_OUTMAXP register is unloaded
from the OUT FIFO. If packets less than the maximum packet size are unloaded,
outpktrdy must be cleared by firmware.
Note: Do not set for High Bandwidth Isochronous endpoints.
6
iso
R/W
0
Isochronous Transfer Enable
0: Enable OUT Bulk and OUT Interrupt transfers.
1: Enable OUT Isochronous transfers.
5
dmareqen
R/W
0
DMA Request Enable
0: Disable DMA for this OUT endpoint.
1: Enable DMA for this OUT endpoint.
4
disnyet/piderror
R/W
R/W0C
0
0
Disable NYET Packets (HS Bulk and HS Interrupt Modes)
0: If the OUT FIFO is full, respond to newly received OUT packets with a NYET (Not
Yet) packet to indicate the FIFO is full.
1: Disable NYET packets. Respond to all received OUT packets with an ACK even
when the FIFO is full.
PID Error Status (Isochronous Mode only)
Automatically set if there is a PID (Packet ID) error in the received OUT packet.
Note: Write 0 to clear.
Note: Ignored in all other modes.
Note: Bit 4 is dual-use and can be addressed by two different names depending on
the endpoint mode.
3
dmareqmode
R/W
0
DMA Request Mode Enable
0: Enable DMA Request Mode 0. A DMA request is generated after each OUT
packet is received.
1: Enable DMA Request Mode 1. A DMA request is generated only when a packet
of USBHS_OUTMAXP.maxpacketsize is received.
2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
dpktbufdis
R/W
0
Double Packet Buffering Disable
0: Enable double packet buffering. Firmware must configure the FIFO and packet
size.
1: Disable double packet buffering.
0
incomprx
R
0
Incomplete Isochronous Packet Received Error Status
High Bandwidth Isochronous Mode:
Automatically set if an incomplete packet is received in the OUT FIFO. Automatically
cleared when USBHS_OUTCSRL.outpktrdy is cleared.
Bulk or Interrupt Modes:
Always reads 0.
Note: Endpoint 1 to 11 have a memory mapped version of this register selected using the USBHS_INDEX register.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English