Maxim Integrated MAX32665 - Table 17-5: Pulse Train Engine Interrupt Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 361 of 457
PT Stopped Interrupt Flag Register
PTG_INTFL
[0x0008]
Bits
Field
Access
Reset
Description
0
pt0
R/W1C
0
PT0 Stopped Status Flag
This bit is set to 1 by hardware when the corresponding pulse train is in Pulse Train
Mode and the loop counter reaches 0. In Square Wave mode, this field is not used.
Write 1 to clear.
1: Pulse Train is stopped.
Table 17-5: Pulse Train Engine Interrupt Enable Register
PT Interrupt Enable Register
PTG_INTEN
[0x000C]
Bits
Field
Access
Reset
Description
31:16
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
15
pt15
R/W
0
PT15 Interrupt Enable
0: Disabled.
1: Enabled.
14
pt14
R/W
0
PT14 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.
13
pt13
R/W
0
PT13 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.
12
pt12
R/W
0
PT12 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.
11
pt11
R/W
0
PT11 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.
10
pt10
R/W
0
PT10 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.
9
pt9
R/W
0
PT9 Interrupt Enable
Write 1 to enable the interrupt for the corresponding PT when the flag is set in the
PTG_INTFL register.
0: Disabled.
1: Enabled.