MAX32665-MAX32668 User Guide
Maxim Integrated Page 292 of 457
The timeout feature is disabled when I2Cn_TIMEOUT.to = 0 and is enabled for any non-zero value. When the timeout is
enabled, the timeout timer starts counting when the I
2
C peripheral hardware drives SCL low and is reset by the I
2
C
peripheral hardware when the SCL line is released.
The timeout counter only monitors if the I
2
C peripheral hardware is driving the SCL line low. It does not monitor if an
external I
2
C device is actively holding the SCL line low. The timeout counter also does not monitor the status of the SDA line.
If the timeout timer expires, a bus error condition has occurred. When a timeout error occurs, the I
2
C peripheral hardware
releases the SCL and SDA lines and sets the timeout error interrupt flag to 1 (I2Cn_INT_FL0.toeri = 1).
For applications where the device may hold the SCL line low longer than the maximum timeout supported, the timeout can
be disabled by setting the timeout field to 0 (I2Cn_TIMEOUT.to = 0).
13.4.14 I
2
C DMA Control
There are independent DMA channels for each TX FIFO and each RX FIFO. DMA activity is triggered by the TX FIFO
(I2Cn_TX_CTRL0.txth) and RX FIFO (I2Cn_RX_CTRL0.rxth) threshold levels.
When the TX FIFO byte count (I2Cn_TX_CTRL1.txfifo) is less than or equal to the TX FIFO Threshold Level
I2Cn_TX_CTRL0.txth, then the DMA transfers data into the TX FIFO according to the DMA configuration. To ensure the DMA
does not overflow the TX FIFO, the DMA burst size should be set as follows:
Equation 13-10: DMA Burst Size Calculation for I
2
C Transmit
DMABurstSize TXFIFODepth txth 8 txth
where 0 7
Applications trying to avoid transmit underflow and/or clock stretching should use a smaller burst size and higher
I2Cn_TX_CTRL0.txth setting. This fills up the FIFO more frequently but increases internal bus traffic.
When the RX FIFO count (I2Cn_RX_CTRL1.rxfifo) is greater than or equal to the RX FIFO Threshold Level
I2Cn_RX_CTRL0.rxth, the DMA transfers data out of the RX FIFO according to the DMA configuration. To ensure the DMA
does not underflow the RX FIFO, the DMA burst size should be set as follows:
Equation 13-11: DMA Burst Size Calculation for I
2
C Receive
DMABurstSize rxth
where 1 rxth 8
Applications trying to avoid receive overflow and/or clock stretching should use a smaller burst size and lower
I2Cn_RX_CTRL0.rxth. This results in reading from the Receive FIFO more frequently but increases internal bus traffic.
Note for receive operations, the length of the DMA transaction (in bytes) must be an integer multiple of
I2Cn_RX_CTRL0.rxth. Otherwise, the receive transaction will end with some data still in the RX FIFO, but not enough to
trigger an interrupt to the DMA, leaving the DMA transaction incomplete. One easy way to ensure this for all transaction
lengths is to set burst size to 1 (I2Cn_RX_CTRL0.rxth = 1).
To enable DMA transfers, enable the TX DMA channel (I2Cn_DMA.txen) and/or the RX DMA channel (I2Cn_DMA.rxen).
13.5 Registers
See Table 3-1: APB Peripheral Base Address Map for the I2C0, I2C1, and I2C2 Register Peripheral Base Addresses for BUS 0
and BUS 1.
Table 13-5: I
2
C Registers
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