Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 261 of 457
(UARTn_CTRL0.parity_en=1). Parity can be based on the number of logic high bits or logic low bits in the receive characters
as set in the register bit UARTn_CTRL0.parity_lvl.
Break frames are transmitted by setting the field UARTn_CTRL0.break to 1. A break sets all bits in the frame to 0.
When a break frame is received, two interrupts are available, UARTn_INT_FL.break is set to 1 when the break frame
character is detected. and UARTn_INT_FL.break_end is set when the end of the break character is detected.
Note: A break condition does not set the frame error flag because breaks are not valid UART characters.
12.3 UART Interrupts
Interrupts can be generated for the for the conditions in the following table:
Table 12-1: UART Interrupt Conditions
Interrupt
Condition
TX FIFO Leve
The transmit FIFO level transitions from being greater than to being equal to the set
transmit threshold.
RX FIFO Level
The receive FIFO level less than the set receive threshold.
RX FIFO Overrun
The receive FIFO is full but is still receiving data.
CTS State Change
during hardware
flow control
CTS is deasserted, which tells the UART to pause transmitting data.
CTS is asserted, which tells the UART to resume transmitting data.
RX Parity
error
RX Frame
START or STOP bits were not detected.
RX Timeout
no characters were received within the set timeout period.
Break
Beginning and end of break.
12.4 UART Baud Rate Clock Source
The device can use either the peripheral clock or a fixed 7.3728MHz clock as its source for baud rate generation. The fixed
7.3728MHz clock should be used for the UART bit rate clock generator if the selected system clock (f
SYS_CLK
) does not meet
the bit rate requirements of the application. In practice, the 7.3728MHz clock is ideal for use during low power mode where
the Peripheral Clock is turned off for power conservation. The 7.3728MHz clock can be enabled during low power modes
enabling the microcontroller to send and receive data while in low power mode.
The UART bit rate clock is set using the UARTn_CTRL0.clksel field. The UART defaults to the peripheral clock for the bit rate
generator clock source. Setting UARTn_CTRL0.clksel to 1 selects the 7.3728MHz clock for the bit rate clock source.
The UART always uses the peripheral clock for register access and logic operation.
12.5 UART Baud Rate Calculation
The UART peripheral clock, 

, is used as the input clock to the UART bit rate generator. The following fields are used to
set the target bit rate for the UART instance.
• UARTn_BAUD0.clkdiv: Selects the bit rate clock divisor.
• UARTn_BAUD0.ibaud: Sets the integer portion of the bit rate divisor.
• UARTn_BAUD1.dbaud: Sets the decimal portion of the bit rate divisor.
The equations below are used to determine the values for each of the bit rate fields required to achieve a target bit rate for
the UART instance.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English