MAX32665-MAX32668 User Guide
Maxim Integrated Page 291 of 457
Note: Interactive Receive Mode does not apply to general call address responses or START byte responses.
Note: When enabling Interactive Receive Mode and operating as a slave, clock stretching must remain enabled
(I2Cn_CTRL0.scl_strd = 0).
13.4.12 Clock Stretching
When the I
2
C peripheral requires some response or intervention from the application firmware in order to continue with a
transaction, it will hold SCL low, preventing the transfer from continuing. This is called ‘clock stretching’ or ‘stretching the
clock’. While the I
2
C Bus Specification defines the term ‘clock stretching’ to only apply to a slave device holding the SCL line
low, this section describes situations where the I
2
C peripheral holds the SCL line low in either slave or master mode and
refers to both as clock stretching.
When the I
2
C peripheral stretches the clock, it typically does so in response to either a full RX FIFO during a receive
operation, or an empty TX FIFO during a transmit operation. Necessarily, this occurs before the next data byte begins,
either between the ACK bit and the first data bit or, if at the beginning of a transaction, immediately after a START or
RESTART condition. However, when operating in Interactive Receive Mode (I2Cn_CTRL0.irxm = 1), the peripheral can also
clock stretch before the ACK bit, allowing firmware to decide whether to send an ACK or NACK.
For a transmit operation (as either master or slave), when the TX FIFO is empty, SCL is automatically held low after the ACK
bit and before the next data byte begins. To stop clock stretching and continue the transaction, firmware must write data to
I2Cn_FIFO.data. If operating in master mode, however, instead of sending more data, firmware may also set either
I2Cn_MSTR_MODE.stop or I2Cn_MSTR_MODE.restart to send a STOP or RESTART condition, respectively.
For a receive operation (as either master or slave), when both the RX FIFO and the receive shift register are full, SCL is
automatically held low until at least one data byte is read from the RX FIFO. To stop clock stretching and continue the
transaction, firmware must read data from I2Cn_FIFO.data. If operating in master mode and this is the final byte of the
transaction, as determined by I2Cn_RX_CTRL1.rxcnt, then application firmware must also set either I2Cn_MSTR_MODE.stop
or I2Cn_MSTR_MODE.restart to send a STOP or RESTART condition, respectively. This must be done in addition to reading
from the RX FIFO, since the peripheral cannot start sending the STOP or RESTART until the last data byte has been moved
from the RX shift register into the RX FIFO. (This will occur automatically once there is space in the RX FIFO.)
Note: Since some masters do not support other devices stretching the clock, it is possible to completely disable all clock
stretching during slave mode by setting I2Cn_CTRL0.scl_strd to 1 and clearing I2Cn_CTRL0.irxm to 0. In this case, instead of
clock stretching the I
2
C peripheral sends a NACK if receiving data, or sends 0xFF if transmitting data.
Note: The clock synchronization required to support other I
2
C master or slave devices stretching the clock is built into the
peripheral and requires no intervention from software to operate correctly.
13.4.13 I
2
C Bus Timeout
The Timeout register, I2Cn_TIMEOUT.to, is used to detect bus errors. Equation 13-8 and Equation 13-9 show equations for
calculating the maximum and minimum timeout values based on the value loaded into the I2Cn_TIMEOUT.to field.
Equation 13-8: I
2
C Timeout Maximum
t
TIMEOUT
1
f
I2CCLK
to
3
Due to clock synchronization, the timeout is guaranteed to meet the following minimum time calculation shown in Equation
13-9.
Equation 13-9: I
2
C Timeout Minimum
t
TIMEOUT
1
f
I2CCLK
to
2
To Next Page
Loading...
Need help?
General