Maxim Integrated MAX32665 - Table 12-7: UART Interrupt Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 267 of 457
UART Status
UARTn_STAT
[0x0008]
Bits
Field
Access
Reset
Description
13:8
rx_num
RO
0
Number of characters in the Receive FIFO
Read this field to determine the number of characters in the receive FIFO.
7
tx_full
RO
0
Transmit FIFO Full Status
0: FIFO is not full.
1: FIFO is full.
6
tx_empty
RO
1
Transmit FIFO Empty Status
0: FIFO is not empty.
1: FIFO is empty.
5
rx_full
RO
0
Receive FIFO Full Status
0: FIFO is not full.
1: FIFO is full.
4
rx_empty
RO
1
Receive FIFO Empty Status
0: FIFO is not empty.
1: FIFO is empty.
3
break
RO
0
Break Status
Set while a break condition exists.
0: A break has not been received.
1: A break condition exists.
2
parity
RO
0
Parity Bit State
This field returns the state of the parity bit.
0: Parity bit is 0.
1: Parity bit is 1.
1
rx_busy
RO
0
Receive Busy
This field reads 1 when the UART is receiving data.
0: UART is not actively receiving data.
1: UART is actively receiving data.
0
tx_busy
RO
0
Transmit Busy
This field reads 1 when the UART is transmitting data.
0: UART is not actively transmitting data.
1: UART is transmitting data.
Table 12-7: UART Interrupt Enable Register
UART Interrupt Enable
UARTn_INT_EN
[0x000C]
Bits
Field
Access
Reset
Description
31:10
-
RO
0
Reserved for Future Use
Do not modify this field.
9
break_end
R/W
0
BREAK End Interrupt Enable
Enables the BREAK End Detection interrupt.
0: Disabled.
1: Enabled.
8
rx_to
R/W
0
Receive Timeout Interrupt Enable
0: Disabled.
1: Enabled.
7
break
R/W
0
Received BREAK Interrupt Enable
Enables the BREAK Detection interrupt.
0: Disabled.
1: Enabled.