MAX32665-MAX32668 User Guide
Maxim Integrated Page 335 of 457
16.6.1 Counter Mode Timer Period
The timer period ends on the rising edge of PCLK following TMRn_CNT = TMRn_CMP.
The timer peripheral automatically performs the following actions at the end of the timer period:
1. TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing on selected transitions
of the timer pin.
2. The timer interrupt bit TMRn_INT.irq will be set. An interrupt will be generated if enabled.
16.6.2 Counter Mode Configuration
Configure the timer for Counter mode by doing the following:
1. Set TMRn_CN.ten = 0 to disable the timer.
2. Set TMRn_CN.tmode to 010b to select Counter mode.
3. Configure the timer pin:
a. Configure the pin as a timer input and configure the electrical characteristics as needed.
b. Set TMRn_CN.tpol to match the desired initial (inactive) state.
4. If using the timer interrupt, enable the interrupt and set the interrupt priority.
5. Write an initial value to TMRn_CNT, if desired. The initial value is only used for the first timer period; subsequent
timer periods always reset TMRn_CNT to 1.
6. Write the compare value to TMRn_CMP.
7. Set TMRn_CN.ten = 1 to enable the timer.
In Counter mode, the number of timer input transitions since timer start is calculated using the following equation:
Equation 16-5: Counter Mode Timer Input Transitions
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