MAX32665-MAX32668 User Guide
Maxim Integrated Page 42 of 457
Instruction-Cache Controller 0
Instruction Cache Controller 1
Instruction Cache Controller XIP
External Memory Cache Controller
Analog to Digital Converter
Pulse Train Engine (bus 0)
BTLE Registers and IQ RAMs
Pulse Train Engine (bus 1)
3.5.2 AHB Peripheral Base Address Map
Table 3-2 contains the base address for each of the AHB mapped peripherals. The base address for a given peripheral is the
start of the register map for the peripheral. For a given peripheral, the address for a register within the peripheral is defined
as the AHB peripheral base address plus the registers offset.
To Next Page
Loading...
Need help?
General