MAX32665-MAX32668 User Guide
Maxim Integrated Page 314 of 457
The following FIFO interrupts are supported:
• Transmit FIFO Empty
• Transmit FIFO Threshold
• Receive FIFO Full
• Receive FIFO threshold
• Transmit FIFO Underrun
Slave mode only, master mode stalls the serial clock
• Transmit FIFO Overrun
• Receive FIFO Underrun
• Receive FIFO Overrun (Slave Mode only, Master Mode will stall the clock)
QSPIn supports interrupts for the internal state of the QSPI as well as external signals. The following transmission interrupts
are supported:
• SSn asserted or deasserted
• SPI transaction complete
• Slave mode transaction aborted
• Multi-master fault
The QSPIn port can wake up the microcontroller for low-power modes when the wake event is enabled. QSPIn events that
can wake the microcontroller are:
• Receive FIFO full
• Transmit FIFO empty
• Receive FIFO threshold
• Transmit FIFO threshold
14.5 Registers
See Table 3-1: APB Peripheral Base Address Map for the QSPI0 and QSPI1 Peripheral Base Address. See Table 3-2: AHB
Peripheral Base Address Map for the QSPI2 Peripheral Base Address.
Table 14-6: QSPIn Base Address Offsets, Register Names, Access and Descriptions
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