MAX32665-MAX32668 User Guide
Maxim Integrated Page 167 of 457
8.3 SPI Execute-in-Place RAM (SPIXR)
The SPI Execute-in-Place RAM Master Controller (SPIXR) is an instantiation of the Quad SPI Interface with the following
features:
• Four SPI modes (mode 0, 1, 2, and 3)
• Master mode only support
• Dual SPI Mode with two bidirectional serial data I/O (SDIO) lines
• High Performance Quad SPI Mode with four bidirectional SDIO lines
• Programmable Serial Clock (SCK) frequency and duty cycle with 48MHz maximum
• 32-byte Transmit FIFO, 32-byte Receive FIFO with DMA support backed by a 16KB Data Cache
The SPIXR Master Controller allows the CPU to transparently execute instructions stored in an external SPI SRAM device.
Instructions fetched using the SPIXR Master Controller are cached just like instructions fetched from internal program
memory. You can also use the SPIXR Master Controller to access large amounts of external data that would otherwise
reside in internal data memory.
Prior to using the SPI SRAM device, you must configure the SPIXR interface.
The command used to transfer SPI SRAM data is configured using firmware. Then, the access to SPI SRAM space (either
code execution or data) may be performed by firmware. The AHB transaction initiated by the firmware provides address
and other transaction critical parameters to control the data transfer from the external SPI SRAM.
Care should be exercised when choosing the correct configuration and command to support the speed of data transfer. The
SPIXR Master Controller provides SCK periods as fast as the AHB clock speed divided by two. The external SPI SRAM
configuration to support data transfer rates must be performed by the SPIXR Master Controller.
To Next Page
Loading...