Maxim Integrated MAX32665 - Table 8-93: SDHC Preset Value 0 to Preset Value 7 Registers; Table 8-94: SDHC Slot Interrupt Status Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 220 of 457
Table 8-93: SDHC Preset Value 0 to Preset Value 7 Registers
Preset Value 0 for Initialization
SDHC_PRESET_0
[0x0060]
Preset Value 1 for Initialization
SDHC_PRESET_1
[0x0062]
Preset Value 2 for Initialization
SDHC_PRESET_2
[0x0064]
Preset Value 3 for Initialization
SDHC_PRESET_3
[0x0066]
Preset Value 4 for Initialization
SDHC_PRESET_4
[0x0068]
Preset Value 5 for Initialization
SDHC_PRESET_5
[0x006A]
Preset Value 6 for Initialization
SDHC_PRESET_6
[0x006C]
Preset Value 7 for Initialization
SDHC_PRESET_7
[0x006E]
Bits
Name
Access
Reset
Description
15:14
driver_strength
RO
1
Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. This field is not
used for 3.3V signaling.
0b00: Driver Type B is selected
0b01: Driver Type A is selected
0b10: Driver Type C is selected
0b11: Driver Type D is selected
13:11
-
RO
0
Reserved for Future Use
Do not modify this field.
10
clk_gen
RO
0
Clock Generator Select Value
0: Programmable clock generator is not supported
9:0
sdclk_freq
RO
-
SDCLK Frequency Select Value
10-bit preset value to set the SDCLK Frequency Select field in the Clock Control
register (SDHC_CLK_CN.upper_sdclk_freq_sel and SDHC_CLK_CN.sdclk_freq_sel)
Table 8-94: SDHC Slot Interrupt Status Register
Slot Interrupt Status Register
SDHC_SLOT_INT
[0x00FC]
Bits
Name
Access
Reset
Description
15:8
-
RO
0
Reserved for Future Use
Do not modify this field.
7:1
-
RO
0
Reserved for Future Use
Do not modify this field.
0
int_signals
RO
0
Interrupt Signals
Indicates the logical OR of Interrupt Signal and Wakeup Signal for the single slot. Only
one slot is defined for the MAX32665—MAX32668, slot 0. Reset by POR and by
software reset for all (SDHC_SW_RESET.reset_all).