Maxim Integrated MAX32665 - Table 4-64: Peripheral Clock Disable Register 1

MAX32665-MAX32668 User Guide
Maxim Integrated Page 102 of 457
Reset 1
GCR_RST1
[0x0044]
Bits
Field
Access
Reset
Description
7
owire
R/W
0
One-Wire Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
6
sdhc
R/W
0
SDHC Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
5
-
RO
0
Reserved.
4
xspim
R/W
0
XSPI Master Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
3
spixip
R/W
0
SPI-XIPF Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
2
-
RO
0
Reserved
1
pt
R/W
0
Pulse Train Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
0
i2c1
R/W
0
I2C1 Reset
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
Table 4-64: Peripheral Clock Disable Register 1
Peripheral Clock Disable 1
GCR_PCLK_DIS1
[0x0048]
Bits
Field
Access
Reset
Description
31
cpu1
R/W
1
CPU1 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
30
-
RO
-
Reserved
Do not modify this field.
29
wdt2
R/W
1
WDT2 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
28
wdt1
R/W
1
Watchdog Timer 1 Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.