Maxim Integrated MAX32665 - Function Control Registers; Function Control Register Details; Table 4-76: Function Control Register Summary; Table 4-77: Function Control Register 0

MAX32665-MAX32668 User Guide
Maxim Integrated Page 113 of 457
Arm Peripheral Bus Asynchronous Bridge Select
GCR_APB_ASYNC
[0x0084]
Bits
Field
Access
Reset
Description
0
apbasyncI2C0
R/W
0
I2C0 Peripheral Bus Select
The access for this peripheral can be performed via one of two different
peripheral bus configurations. The system PCLK can be used as any of the other
system peripherals that are connected to the APB PCLK domain or a 7.3728MHz
bus can be used. It takes 3 cycles of the 7.3728MHz clock to switch PCLK or 3
cycles of the PCLK clock to switch to 7.37MHz clock. After switching, ensure
enough time before accessing the peripheral registers.
0: PCLK bus selected
1: 7.3728MHz bus selected
4.18 Function Control Registers
See Table 3-1: APB Peripheral Base Address Map for this module's base address. Unless specified otherwise, all fields are
reset only on a system reset or POR, but not a soft reset.
Table 4-76: Function Control Register Summary
Offset
Register
Description
[0x0000]
GCR_FCR
Function Control Register
4.19 Function Control Register Details
Table 4-77: Function Control Register 0
Function Control 0
GCR_FCR
[0x0000]
Bits
Field
Access
Reset
Description
31:26
-
RO
0
Reserved
Do not modify this field.
25
i2c2_scl_filter_en
R/W
0
I2C2 SCL Glitch Filter Enable
0: Disabled
1: Enabled
24
i2c2_sda_filter_en
R/W
0
I2C2 SDA Glitch Filter Enable
0: Disabled
1: Enabled
23
i2c1_scl_filter_en
R/W
0
I2C1 SCL Glitch Filter Enable
0: Disabled
1: Enabled
22
i2c1_sda_filter_en
R/W
0
I2C1 SDA Glitch Filter Enable
0: Disabled
1: Enabled
21
i2c0_scl_filter_en
R/W
0
I2C0 SCL Glitch Filter Enable
0: Disabled
1: Enabled
20
i2c0_sda_filter_en
R/W
0
I2C0 SDA Glitch Filter Enable
0: Disabled
1: Enabled
19:18
-
RO
0
Reserved
Do not modify this field.