Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 418 of 457
USBHS IN Endpoint Lower Control and Status
USBHS_INCSRL
[0x0012]
Bits
Name
Access
Reset
Description
6
clrdatatog
R/W1O
0
Clear IN Endpoint Data Toggle
1: Clear the IN Endpoint data toggle to 0.
Note: Automatically cleared after set.
5
sentstall
R/W0C
0
Read STALL Handshake Sent Status
Automatically set when a STALL handshake is transmitted, at which time the IN
FIFO is flushed, and USBHS_INCSRL.inpktrdy is cleared.
Note: Write a 0 to clear.
4
sendstall
R/W
0
Send STALL Handshake
1: Respond to an IN token with a STALL handshake.
0: Terminate STALL handshake
Note: Ignored for Isochronous transfers.
3
flushfifo
R/W1O
0
Flush Next Packet from IN FIFO
1: Flush the next packet to be transmitted from the IN FIFO. This also clears the bit
field USBHS_INCSRL.inpktrdy. This must only be set when
USBHS_INCSRL.inpktrdy = 1, or FIFO data corruption might occur.
Note: If the IN FIFO contains two packets, set the flushfifo field twice to clear both
packets.
Note: Automatically cleared when the packet is flushed.
2
underrun
R/W0C
0
Read IN FIFO Underrun Error Status
Isochronous Mode: Automatically set if the IN FIFO is empty (inpktrdy = 0), an IN
token has been received, and a zero-length data packet has been sent.
Bulk or Interrupt Modes: Automatically set when an IN token is received, and a
NAK is sent.
Note: Write a 0 to clear.
1
fifonotempty
R/W0C
0
Read FIFO Not Empty Status
Automatically set when there is at least one packet in the IN FIFO.
Note: Write a 0 to clear.
0
inpktrdy
R/W1O
0
IN Packet Ready
1: Write a 1 after writing a data packet to the IN FIFO.
Automatically cleared when the data packet is transmitted. If double-buffering is
enabled, this bit is automatically cleared when there is space for a second packet in
the FIFO.
Note: This bit field is also controlled by USBHS_INCSRU.autoset.
21.12.5 USBHS Endpoint 0 Control Status Register
Table 21-20: USBHS Endpoint 0 Control Status Register
USBHS Endpoint 0 Control Status
USBHS_CSR0
[0x0012]
Bits
Name
Access
Reset
Description
7
servicedsetupend
R/W1C
0
Clear EP0 Setup End Bit
Write a 1 to clear the setupend bit.
Note: Automatically cleared after being set.
6
servicedoutpktrdy
R/W1C
0
Clear EP0 Out Packet Ready Bit
Write a 1 to clear the outpktrdy bit (below).
Note: Automatically cleared after being set.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English