MAX32665-MAX32668 User Guide
Maxim Integrated Page 147 of 457
Multiple headers and payloads are written to the Transmit FIFO for consecutive execution. As an example, complete the
following steps to set up the external SPI flash bus width using the SPIXF Master Controller:
1. Configure the SPIXF Master Controller so it can communicate with the default configuration of the external SPI flash
chosen using the appropriate register and header settings.
2. Write the header and initial payload to the Transmit FIFO to send configuration of the data width
(single/dual/quad) to the external SPI flash. This might require multiple commands to write status registers of the
external flash device or to send specific commands.
3. Write header and payload to the Transmit FIFO to complete subsequent commands (read/write external SPI flash
registers and program external SPI flash) using the new external SPI flash IO configuration.
4. Enable the SPIXF Master Controller to send commands to the external SPI flash.
8.2.1.1.4 Clock Phase and Polarity Control
The SPIXF Master Controller and the SPIXF Master support configuration of SCK phase and polarity:
• Clock polarity (CLKPOL) selects an active low/high clock and has no effect on the transfer format
• Clock phase (PHASE) selects one of two different transfer formats
The master always places data on the MOSI line a half cycle before the SCK edge for the slave to latch the data.
Table 8-2 details the SCK phase and polarity combinations supported.See SPIXFC_CFG.mode register.
Table 8-2: Clock Polarity and Phase Combinations
Note: Do not change the clock phase and polarity control while executing or reading from SPIXF space. This configuration
should ideally be done prior to SPIXF transactions and remain unchanged while reading or executing from SPIXF space. If the
clock phase and polarity need to be changed after the SPIXF slave select is active, the user must not be executing from SPIXF
space, and the SPIXF block should be reset by setting GCR_RST1.spixip = 1.
8.2.1.1.5 Serial Clock Configuration
The output clock speed and pulse width can be controlled with the SPIXFC_CFG.hiclk and SPIXFC_CFG.loclk register fields.
SPIXFC_CFG.loclk where,
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