Maxim Integrated MAX32665 - Table 4-56: System Clock Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 90 of 457
Reset 0
GCR_RST0
[0x0004]
Bits
Field
Access
Reset
Description
3
gpio1
R/W
0
GPIO1 Reset
Write 1 to reset.
0: Not in reset
1: Reset in progress.
3
gpio1
R/W
0
GPIO1 Reset
Write 1 to reset.
0: Not in reset
1: Reset in progress.
2
gpio0
R/W
0
GPIO0 Reset
Write 1 to reset.
0: Not in reset
1: Reset in progress.
1
wdt0
R/W
0
Watchdog Timer 0 Reset
Write 1 to reset.
0: Not in reset
1: Reset in progress.
0
dma0
R/W
0
DMA0 Access Block
Write 1 to reset.
0: Not in reset
1: Reset in progress.
Table 4-56: System Clock Control Register
System Clock Control
GCR_CLK_CTRL
[0x0008]
Bits
Field
Access
Reset
Description
31:29
-
RO
0b011
Reserved
Do not modify this field.
28
hirc7m_rdy
RO
0
7.3728MHz Internal Oscillator Ready Status
0: Not ready or not enabled.
1: Oscillator ready.
27
hircmm_rdy
RO
0
96MHz Internal Oscillator Ready Status
0: Not ready or not enabled.
1: Oscillator ready.
26
hirc60m_rdy
RO
1
60MHz Internal Oscillator Ready Status
0: Not ready or not enabled.
1: Oscillator ready.
25
x32k_rdy
RO
0
32.768kHz External Oscillator Ready Status
0: Not ready or not enabled.
1: Oscillator ready.
24
x32M_rdy
RO
0
32MHz Bluetooth Oscillator Ready Status
0: Not ready or not enabled.
1: Oscillator ready.
23:22
-
RO
0
Reserved
Do not modify this field.