MAX32665-MAX32668 User Guide
Maxim Integrated Page 230 of 457
9.6 DMA Interrupts
Enable interrupts for each channel by setting DMACn_CN.chien. When an interrupt for a channel is pending, the
corresponding DMACn_INT.ipend = 1. Set the corresponding enable bit to cause an interrupt when the flag is set.
A channel interrupt (DMACHn_ST.ipend = 1) is caused by:
• DMACHn_CFG.ctzien = 1
If enabled all CTZ occurrences set the DMACHn_ST.ipend bit.
• DMACHn_CFG.chdien = 1
If enabled, any clearing of the DMACHn_ST.ch_st bit sets the DMACHn_ST.ipend bit. Examine the DMACHn_ST
register to determine which reasons caused the disable. The DMACHn_CFG.chdien bit also enables the
DMACHn_ST.to_st bit. The DMACHn_ST.to_st bit does not clear the DMACHn_ST.ch_st bit.
To clear the channel interrupt, write 1 to the cause of the interrupt (the DMACHn_ST.ctz_st, DMACHn_ST.rld_st,
DMACHn_ST.bus_err, or DMACHn_ST.to_st bits).
When running in normal mode without buffer chaining (DMACHn_CFG.rlden = 0), set the DMACHn_CFG.chdien bit only. An
interrupt is generated upon DMA completion or an error condition (bus error or timeout error).
When running in buffer chaining mode (DMACHn_CFG.rlden = 1), set both the DMACHn_CFG.chdien and
DMACHn_CFG.ctzien bits. The CTZ interrupts occur on completion of each DMA (count reaches zero and reload occurs). The
setting of DMACHn_CFG.chdien ensures that an error condition generates an interrupt. If DMACHn_CFG.ctzien = 0, then the
only interrupt occurs when the DMA completes and DMACHn_CFG.rlden = 0 (final DMA).
9.7 Channel Timeout Detect
Each channel can optionally generate an interrupt when its associated peripheral does not request a transfer in a user-
configurable period of time. When the timeout start conditions are met, an internal 10-bit counter begins incrementing at a
frequency determined by the AHB clock, DMACHn_CFG.to_prescale, and DMACHn_CFG.to_period shown in Table 9-5: DMA
Channel Timeout Configuration. A channel timeout event is generated if the timer is not reset by one of the events listed
below before the timeout period expires.
Table 9-5: DMA Channel Timeout Configuration
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