Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 290 of 457
When TX FIFO Preloading is enabled, the software controls ACKs to the external master using the TX Ready
(I2Cn_TX_CTRL1.txrdy) bit. When I2Cn_TX_CTRL1.txrdy is set to 0, hardware automatically NACKs all read transactions from
the Master. Setting I2Cn_TX_CTRL1.txrdy to 1 sends an ACK to the Master on the next read transaction and transmits the
data in the TX FIFO. Preloading the TX FIFO should be complete prior to setting the I2Cn_TX_CTRL1.txrdy field to 1.
The required steps for implementing TX FIFO Preloading in an application are as follow:
1. Enable TX FIFO Preloading by setting I2Cn_TXCTRL1.txpreld to 1.
a. This will automatically clear I2Cn_TX_CTRL1.txrdy to 0
2. If the TX FIFO Lockout Flag (I2Cn_INT_FL0.txloi) is set to 1, write 1 to clear the flag and enable writes to the TX
FIFO.
3. Enable DMA or Interrupts if required.
4. Load the TX FIFO with the data to send when the Master sends the next read request.
5. Set I2Cn_TX_CTRL1.txrdy to 1 to automatically let the hardware send the preloaded FIFO on the next read from a
Master.
6. I2Cn_TX_CTRL1.txrdy is cleared by hardware once it finishes transmitting the first byte, and data is transmitted
from the TX FIFO. Once cleared, the application firmware may repeat the Preloading process or disable TX FIFO
Preloading.
Note: To prevent the preloaded data from being cleared when the master tries to read it, firmware must at least set
I2Cn_TX_CTRL0.samrtxafdis to 1, disabling autoflush on READ address match. The software will determine whether the
other autoflush disable bits should be set. For example, if a master uses I
2
C WRITE transactions to determine what data the
slave should send in the following READ transactions, then software can clear I2Cn_TX_CTRL0.samwtxafdis to 0. Then when
a WRITE occurs, the TX FIFO is flushed, giving firmware time to load the new data. For the READ transaction, the external
master can poll the slave address until the new data has been loaded and I2Cn_TX_CTRL1.txrdy is set, at which point the
peripheral responds with an ACK.
13.4.11 Interactive Receive Mode (IRXM)
In some situations, the I
2
C might want to inspect and respond to each byte of received data. In this case, Interactive Receive
Mode (IRXM) can be used. Interactive Receive Mode is enabled by setting I2Cn_CTRL0.irxm=1. If Interactive Receive Mode
is enabled, it must occur before any I
2
C transfer is initiated.
When Interactive Receive Mode (IRXM) is enabled, after every data byte received the I
2
C peripheral automatically holds SCL
low before the ACK bit. Additionally, after the 8th SCL falling edge, the I
2
C peripheral sets the IRXM Interrupt Status Flag
(I2Cn_INT_FL0.irxmi = 1). Application firmware must read the data and generate a response (ACK or NACK) by setting the
IRXM Acknowledge (I2Cn_CTRL0.ack) bit accordingly. Send an ACK by clearing the I2Cn_CTRL0.ack bit to 0. Send a NACK by
setting the I2Cn_CTRL0.ack bit to 1.
After setting the I2Cn_CTRL0.ack bit, clear the IRXM interrupt flag. Write 1 to I2Cn_INT_FL0.irxmi to clear the interrupt flag.
When the IRXM interrupt flag is cleared, the I
2
C peripheral hardware releases the SCL line and sends the I2Cn_CTRL0.ack on
the SDA line.
While the I
2
C peripheral is waiting for the application firmware to clear the I2Cn_INT_FL0.irxmi flag, firmware can disable
Interactive Receive Mode and, if operating as a master, load the remaining number of bytes to be received for the
transaction. This allows firmware to examine the initial bytes of a transaction, which might be a command, and then disable
Interactive Receive Mode to receive the remaining bytes in normal operation.
During IRXM, received data is not placed in the RX FIFO. Instead, the I2Cn_FIFO address is repurposed to directly read the
receive shift register, bypassing the RX FIFO. Therefore, before disabling Interactive Receive Mode, firmware must first read
the data byte from I2Cn_FIFO.data. If the IRXM byte is not read, the byte is lost and the next read from the RX FIFO returns
0xFF.
Note: Interactive Receive Mode does not apply to address bytes, only to data bytes.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English