Maxim Integrated MAX32665 - Register Details; Table 6-9: GPIO Port N Configuration Enable Bit 0 Register; Table 6-10: GPIO Port N Configuration Enable Atomic Set Bit 0 Register; Table 6-11: GPIO Port N Configuration Enable Atomic Set Bit 0 Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 126 of 457
Offset
Register
Name
[0x00B4]
GPIOn_DS_SEL1
GPIO Port n Output Drive strength selection register 1
[0x00B8]
GPIOn_PS
GPIO Port n Pulldown/Pullup strength select register
[0x00C0]
GPIOn_VSSEL
GPIO0 Port n Voltage select register
6.5 Register Details
Table 6-9: GPIO Port n Configuration Enable Bit 0 Register
GPIO Port n Configuration Enable Bit 0
GPIOn_EN0
[0x0000]
Bits
Field
Access
Reset
Description
31:0
-
R/W
1
GPIO Configuration Enable, Bit 0
This bit, in conjunction with bits in Table 6-3: MAX32665—MAX32668 GPIO Pin
Configuration, configures the corresponding device pin for digital I/O or an alternate
function modes. This field can be modified directly by writing to this register or
indirectly through GPIOn_EN0_SET or GPIOn_EN0_CLR.
Some GPIO are not implemented all devices. The bits associated with
unimplemented GPIO should not be changed from their default value.
This bit’s setting does not affect input and interrupt functionality of the associated
pin.
Table 6-10: GPIO Port n Configuration Enable Atomic Set Bit 0 Register
GPIO Port n Configuration Enable Atomic Set Bit 0
GPIOn_EN0_SET
[0x0004]
Bits
Field
Access
Reset
Description
31:0
-
R/W
0
GPIO Configuration Enable Atomic Set, Bit 0
Writing 1 to one or more bits sets the corresponding bits in the GPIOn_EN0 register.
0: No effect.
1: Corresponding bits in GPIOn_EN0 register set to 1.
Table 6-11: GPIO Port n Configuration Enable Atomic Set Bit 0 Register
GPIO Port n Configuration Enable Atomic Clear Bit 0
GPIOn_EN0_CLR
[0x0008]
Bits
Field
Access
Reset
Description
31:0
-
WO
0
GPIO Configuration Enable Atomic Clear, Bit 0
Writing 1 to one or more bits clears the corresponding bits in the GPIOn_EN0
register.
0: No effect.
1: Corresponding bits in GPIOn_EN0 register cleared to 0.
Table 6-12: GPIO Port n Output Enable Register
GPIO Port n Output Enable
GPIOn_OUT_EN
[0x000C]
Bits
Field
Access
Reset
Description
31:0
-
R/W
0
GPIO Output Enable
Set bit to 1 to enable the output driver for the corresponding GPIO pin. A bit can be
enabled directly by writing to this register or indirectly through GPIOn_OUT_EN_SET
or GPIOn_OUT_EN_CLR.
0: Pin is set to input mode; output driver disabled.
1: Pin is set to output mode.